Commits included in published releases. Unpublished intermediate commits are private. Showing matches from the latest 100 commits ending at this release.
soc/core/vexiiriscv: add macsg support (dma based ethernet)
Dolu1990 · Oct 24, 2024, 2:00 PM UTC
375940ad7d12
soc/core/vexiiriscv : bring back xilinx support
Dolu1990 · Oct 15, 2024, 7:36 AM UTC
d5e4f9e9755e
soc/cores/cpu/zynqmp/core.py: add_ethernet: added gt_location required by SGMII
efinix: ifacewriter: add `in_clk_inv` for GPIO INPUT block
Fin Maaß · Sep 25, 2024, 9:00 AM UTC
2c3536720cea
efinix: ifacewriter: fix `out_reg` in GPIO INOUT block
Fin Maaß · Sep 25, 2024, 8:59 AM UTC
10ab1b76c0fd
build/efinix/common: Disable SDRInput for now since breaking designs, needs to be investigated.
Florent Kermarrec · Sep 26, 2024, 10:58 AM UTC
b135f7151216
build/efinix/common: Update EfinixSDRInputImpl and minor cleanup.
Florent Kermarrec · Sep 26, 2024, 9:50 AM UTC
b5e91473b761
Merge pull request #2081 from VOGL-electronic/build_efinix_add_sdr_input
enjoy-digital · Sep 26, 2024, 9:43 AM UTC
0e337e20795c
Merge pull request #2078 from VOGL-electronic/efinix_add_ipm
enjoy-digital · Sep 26, 2024, 9:42 AM UTC
a19fbb70c4fd
Merge pull request #2082 from enjoy-digital/efinix_iface_signal_names
enjoy-digital · Sep 26, 2024, 9:42 AM UTC
b11cc8c3eb7f
build/efinix/common: Deprecate passing clk as str to avoid previous approach with pre-generated names.
Florent Kermarrec · Sep 26, 2024, 8:37 AM UTC
39d292a3c7b5
build/efinix/common: Directly pass ClockSignal/Signal to blocks and let the build resolve names.
Florent Kermarrec · Sep 26, 2024, 8:14 AM UTC
a3a55fc8fb30
build/efinix/efinity: Add resolve_iface_signal_names method to automatically resolve ClockSignal/Signal names passed in the blocks.
Florent Kermarrec · Sep 26, 2024, 8:12 AM UTC
fde9d2e4ad3c
build: efinix: common.py; add `SDRInput`
Fin Maaß · Sep 25, 2024, 3:17 PM UTC
61f715e6e77e
soc/cores/vexriscv_smp: Add the generation of the default sim config (https://github.com/litex-hub/linux-on-litex-vexriscv/issues/405)
Dolu1990 · Sep 25, 2024, 8:38 AM UTC
c3e87367c32c
build/sim/core/veril.cpp: Flush trace file on finish, fix issue with empty .fst dumps with short simulations.
Florent Kermarrec · Sep 25, 2024, 6:53 AM UTC
b86d76baed3e
build: efinix: add function to add ip
Fin Maaß · Sep 24, 2024, 9:59 AM UTC
8a6264c4f605
soc/interconnect/stream: Add Delay module.
Florent Kermarrec · Sep 23, 2024, 10:23 AM UTC
c95a6e041c21
CHANGES.md: Update.
Florent Kermarrec · Sep 20, 2024, 11:00 AM UTC
b2f63b37cccb
CONTRIBUTORS: Update.
Florent Kermarrec · Sep 20, 2024, 10:43 AM UTC
427ec10cc434
LICENSE: Bump year.
Florent Kermarrec · Sep 20, 2024, 10:39 AM UTC
726d39f40d64
Merge pull request #2075 from trabucayre/efinix_clkinput_signal
enjoy-digital · Sep 19, 2024, 9:59 AM UTC
baff4c69fe95
Merge pull request #2076 from trabucayre/xc7s_jtag
enjoy-digital · Sep 19, 2024, 9:53 AM UTC
033ec13f089c
soc/core/hyperbus: Avoid combinatorial loop on write bursts (Reported when building with Vivado).
Florent Kermarrec · Sep 19, 2024, 9:10 AM UTC
6e9dffdbf5f6
soc/cores/cpu/vexiirscv: Add standard variant to allow compilation without specifying --cpu-variant.
Florent Kermarrec · Sep 19, 2024, 7:21 AM UTC
ad2c3fcea71d
build/efinix/ifacewriter.py: allows the use of ClockSignal for IN_CLK_PIN (gpio)
Gwenhael Goavec-Merou · Sep 19, 2024, 7:14 AM UTC
f1e1f3530ed1
build/efinix/common.py: ClkInput: added ClockSignal support
Gwenhael Goavec-Merou · Sep 18, 2024, 1:25 PM UTC
aca959b059ff
build/xilinx/platform.py: added xc7s to the list of device supporting jtag access
Gwenhael Goavec-Merou · Sep 19, 2024, 4:49 AM UTC
e072156b937e
soc/cores/jtag.py: added Spartan7 definition for BSCANE2
Gwenhael Goavec-Merou · Sep 19, 2024, 4:49 AM UTC
fc68f031a16d
Merge pull request #1974 from motec-research/dts_zephyr_updates
enjoy-digital · Sep 17, 2024, 12:58 PM UTC
9bacbe130b2c
soc/interconnect/stream: Add optional CSR to Multiplexer/Demultiplexer and Crossbar module with mux and demux.
Florent Kermarrec · Sep 13, 2024, 5:21 PM UTC
a350d2e9092c
build/xilinx/vivado: Fix typo.
Florent Kermarrec · Sep 13, 2024, 8:39 AM UTC
2a19a61e054a
Merge pull request #2069 from VOGL-electronic/fix-sim-ethernet
enjoy-digital · Sep 13, 2024, 6:36 AM UTC
99550809b34e
build/xilinx/vivado: Rename opt_directive to vivado_opt_directive for consistency with other directives.
Florent Kermarrec · Sep 12, 2024, 4:04 PM UTC
dc8c1bd9cd92
integration/soc/add_etherbone: Allow 64-bit support now that validated.
Florent Kermarrec · Sep 12, 2024, 11:38 AM UTC
203c9816b289
sim: add HW_PREAMBLE_CRC for ethernet
Matthias Breithaupt · Sep 12, 2024, 6:22 AM UTC
2fd8c2cd613c
Merge pull request #2066 from VOGL-electronic/soc.py_ethernet_mac
enjoy-digital · Sep 11, 2024, 9:54 AM UTC
b41a526e81ad
Merge pull request #2065 from VOGL-electronic/bios_little_warning_fix
enjoy-digital · Sep 11, 2024, 9:53 AM UTC
11c7b69fd46a
soc.py: add_ethernet: add mac addr constant
Fin Maaß · Sep 11, 2024, 9:21 AM UTC
7b3f1509d1f7
bios: boot.c: fix warnings
Fin Maaß · Sep 11, 2024, 9:15 AM UTC
3966e3438cd2
Merge pull request #2060 from Dolu1990/efinix-rework
Gwenhael Goavec-Merou · Sep 10, 2024, 4:40 PM UTC
dc8b74cc586f
soc/cores/clock/efinix.py: fill platform.clks with clkout mapping cd/clk_out_name. litex/build/efinix/ifacewriter.py: generate_lvds: when slow_clk/fast_clk are ClockSignal uses platform.clks to map between domain and signal name
Gwenhael Goavec-Merou · Sep 10, 2024, 4:07 PM UTC
a80f290d80a2
soc/cores/clock/efinix.py: register_clkin: uses clkin.name_override as input_signal name when name is not provided and PLL is configured in CORE or INTERNAL mode, create_clkout: added PLL name in clk_name str
Gwenhael Goavec-Merou · Sep 10, 2024, 4:01 PM UTC
ad09ffc1506d
build/efinix/common.py: replaced i as str by a ClockDomain
Gwenhael Goavec-Merou · Sep 10, 2024, 3:56 PM UTC
109ae17e9e06
soc/interconnect/wishbone: Add Bypass mode on Cache when cachesize == 0 and similar data_widths.
Florent Kermarrec · Sep 9, 2024, 4:18 PM UTC
458e0057f272
soc/interconnect/wishbone: Cosmetic cleanup on Cache.
Florent Kermarrec · Sep 9, 2024, 4:16 PM UTC
5cd1a5708095
Merge pull request #2059 from Dolu1990/vexii-clk-video
enjoy-digital · Sep 9, 2024, 12:12 PM UTC
e06045c57662
core/vexiiriscv: improve l2 timings
Dolu1990 · Sep 6, 2024, 2:05 PM UTC
2db93c8e7878
Merge pull request #2058 from VOGL-electronic/bios_add_spiram