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Commits included in published releases. Unpublished intermediate commits are private. Showing matches from the latest 100 commits ending at this release.

cores/cpu/vexiiriscv: Add PMP support

Dolu1990 · Nov 26, 2024, 4:40 PM UTC

070c4cd38754

build/altera/quartus: Add .svf generation (required for now with openFPGALoader) and create_rbf property.

Florent Kermarrec · Nov 26, 2024, 3:11 PM UTC

29c5a1db8387

Merge pull request #2125 from trabucayre/ecp5_diamond_tristate

enjoy-digital · Nov 18, 2024, 11:40 AM UTC

10dcc736767d

soc/integration/soc_core: Fix with_uartbone changes.

Florent Kermarrec · Nov 18, 2024, 10:07 AM UTC

52148c7aadfe

build/lattice/common.py: added Tristate support for ECP5 when build with diamond

Gwenhael Goavec-Merou · Nov 17, 2024, 10:32 AM UTC

211ce59df49d

Merge pull request #2100 from VOGL-electronic/efinix_io_optimize

enjoy-digital · Nov 15, 2024, 8:38 AM UTC

8041969e0072

Merge pull request #2122 from acceleratedtech/accelerated/uart-dynamic-baudrate-for-upstream

enjoy-digital · Nov 15, 2024, 8:36 AM UTC

8399c919bd11

Merge pull request #2101 from VOGL-electronic/bios_spi_fix

enjoy-digital · Nov 13, 2024, 10:12 AM UTC

2b3fd723a2d9

Merge pull request #2119 from long-pham/pr_useAllCPUCores

enjoy-digital · Nov 12, 2024, 8:45 PM UTC

0f45ea221efc

Merge pull request #2118 from long-pham/pr_openfpgaloader

enjoy-digital · Nov 12, 2024, 8:40 PM UTC

e9e0140c742a

Merge pull request #2117 from long-pham/main

enjoy-digital · Nov 12, 2024, 8:40 PM UTC

8ece14849a30

Merge pull request #2123 from trabucayre/vhd2vconverter_libraries

enjoy-digital · Nov 12, 2024, 8:38 PM UTC

d7a8743f2098

Merge pull request #2120 from juiceRv/fix/veril-fst-trace

enjoy-digital · Nov 12, 2024, 8:37 PM UTC

f056f37c2985

build/vhd2v_converter.py: allows users to pass a list of libraries files to compile before convert HDL.

Gwenhael Goavec-Merou · Nov 9, 2024, 6:55 AM UTC

f731b36c9b99

feat: add uart_with_dynamic_baudrate to SoCCore

Jamey Hicks · Oct 28, 2024, 7:04 PM UTC

f53178d71240

Fixes: Fix no close trace file when the sim is finished

Li.XiongHui · Nov 7, 2024, 6:21 AM UTC

5fa144ec3aa5

Switch to using MMCME4_ADV in USPMMCM to enable finer-grained clock output control

Long Pham · Nov 6, 2024, 9:48 PM UTC

9cc8bf98660b

Merge pull request #2115 from CKeilbar/soc-region-check-fix

enjoy-digital · Nov 6, 2024, 9:29 PM UTC

8b4949edcdc1

soc/cores/cpu/urv: Add DataBusToWishbone and use it.

Florent Kermarrec · Nov 6, 2024, 8:59 PM UTC

de9d3ab3143c

soc/cores/cpu/urv: Add InstructionBusToWishbone and use it.

Florent Kermarrec · Nov 6, 2024, 8:49 PM UTC

2b3913982cde

Enhance software build performance by utilizing all available CPU cores in the builder

Long Pham · Nov 6, 2024, 7:35 PM UTC

d8e168a81fb6

Add FTDI serial number option to openfpgaloader, useful when multiple similar boards are connected for CI/CD

Long Pham · Nov 6, 2024, 7:25 PM UTC

935326e66cef

soc/cores/cpu/urv: Fix add_sources.

Florent Kermarrec · Nov 5, 2024, 4:33 PM UTC

1204cfda9d18

cpu/urv: Fix Instruction Bus conversion to Wishbone and only keep it now that working.

Florent Kermarrec · Nov 5, 2024, 3:46 PM UTC

20b0e98fe019

Fix SOC region range check

Chris Keilbart · Nov 4, 2024, 8:01 PM UTC

e9613499eaa4

soc/cores/jtag: Fix/Test p_init/p_INIT workaround.

Florent Kermarrec · Nov 4, 2024, 1:34 PM UTC

0170462fe8a6

Merge pull request #2113 from trabucayre/toolchain_diamond_sdc

enjoy-digital · Nov 4, 2024, 11:53 AM UTC

3f3249cdf064

litex/build/lattice/diamond, platform: allows users to add custom sdc files

Gwenhael Goavec-Merou · Nov 4, 2024, 11:42 AM UTC

47e8b0273f1d

soc/cores/jtag: Add p_INIT/p_init workaround on ECP5JTAG to support Diamond and Trellis toolchains without manual changes.

Florent Kermarrec · Nov 4, 2024, 11:40 AM UTC

175e63ac4cdf

test/test_led: Comment out TestWS1812 test since seems broken, will need to be investigated/fixed.

Florent Kermarrec · Oct 28, 2024, 8:51 PM UTC

4368d5a9ede3

soc/cores/jtag: Revert p_INIT since not tested.

Florent Kermarrec · Oct 28, 2024, 7:05 PM UTC

61ab30a739ed

Merge pull request #2097 from trabucayre/build_diamond_addition

enjoy-digital · Oct 28, 2024, 7:05 PM UTC

10184ad325f7

Merge pull request #2102 from Dolu1990/vexiiriscv-macsg

enjoy-digital · Oct 28, 2024, 7:03 PM UTC

23df960859c5

Merge branch 'master' into vexiiriscv-macsg

enjoy-digital · Oct 28, 2024, 7:02 PM UTC

dd092863f81c

Merge pull request #2104 from andelf/fix/ws2812-of-1-led

enjoy-digital · Oct 28, 2024, 6:53 PM UTC

18714dfca3d2

Merge pull request #2099 from VOGL-electronic/vexiiriscv_sbi

Dolu1990 · Oct 25, 2024, 12:26 PM UTC

59fc1caac4da

vexiiriscv: have opensbi behind a option

Fin Maaß · Oct 18, 2024, 5:58 AM UTC

773fb3407920

Fixes #2103: calculate memory depth for WS2812

Andelf · Oct 25, 2024, 3:43 AM UTC

8c7e510473b6

Merge remote-tracking branch 'origin/master' into wuff

Dolu1990 · Oct 24, 2024, 2:02 PM UTC

24db36ced579

soc/core/vexiiriscv: add macsg support (dma based ethernet)

Dolu1990 · Oct 24, 2024, 2:00 PM UTC

375940ad7d12

bios: litespi: add newline to debug output

Fin Maaß · Oct 24, 2024, 1:12 PM UTC

d7bf75a75c95

bios: litespi: clear rx queue after write

Fin Maaß · Oct 24, 2024, 1:10 PM UTC

63fa4fda85f1

build: efinix: use constant output option

Fin Maaß · Oct 23, 2024, 9:55 AM UTC

54973eb9cb2c

build: io: SDRTristate: move check

Fin Maaß · Oct 23, 2024, 9:18 AM UTC

2d96e99494de

efinix: ifacewriter: fix in output

Fin Maaß · Oct 23, 2024, 9:10 AM UTC

70f4a349e525

efinix: ifacewriter: gpio: share common code

Fin Maaß · Oct 23, 2024, 9:08 AM UTC

d6eec8e76d13

Merge pull request #2098 from enjoy-digital/urv

enjoy-digital · Oct 17, 2024, 5:45 PM UTC

c1225736a8c3

CHANGES.md: Update.

Florent Kermarrec · Oct 17, 2024, 3:45 PM UTC

5f463dba87d0

soc/cores/cpu/urv: Move ROM init to builder and allow switching between classical ROM or ROM integrated in CPU.

Florent Kermarrec · Oct 17, 2024, 3:44 PM UTC

aab8912f5a51

soc/cores/cpu/urv: Able to boot LiteX BIOS with im bus connected to synchronous memory. - Replace im bus wishbone adaptation with synchronous memory (for now and initial tests). - Correctly handle dm bus wishbone adaptation (Added FIFO).

Florent Kermarrec · Oct 17, 2024, 2:54 PM UTC

9449d25911b8

soc/cores/cpu: Add initial uRV CPU support (not yet working).

Florent Kermarrec · Oct 16, 2024, 8:24 PM UTC

edb56e73aa3c

litex/soc/cores/jtag.py: lattice target: INIT -> init (otherwise fails with diamond)

Gwenhael Goavec-Merou · Oct 16, 2024, 11:47 AM UTC

06f9f9780da1

build/lattice/diamond.py,platform.py: allows adding custom strategy

Gwenhael Goavec-Merou · Oct 16, 2024, 11:46 AM UTC

ea81314866f9

build/lattice/diamond.py,platform.py: allows adding lattice's IPs

Gwenhael Goavec-Merou · Oct 16, 2024, 11:45 AM UTC

331e1938c927

build/lattice/diamond.py: allows adding addition ldf commands in tcl

Gwenhael Goavec-Merou · Oct 16, 2024, 11:44 AM UTC

c4943c1c5d13

CHANGES.md: Update.

Florent Kermarrec · Oct 15, 2024, 10:54 AM UTC

c82fddf63591

soc/core/vexiiriscv : bring back xilinx support

Dolu1990 · Oct 15, 2024, 7:36 AM UTC

d5e4f9e9755e

soc/cores/cpu/zynqmp/core.py: add_ethernet: added gt_location required by SGMII

Gwenhael Goavec-Merou · Oct 10, 2024, 3:28 PM UTC

7f04cafe0841

soc/cores/cpu/zynqmp/core.py: added missing pps signals

Gwenhael Goavec-Merou · Oct 10, 2024, 3:26 PM UTC

2935b7afb1e0

CHANGES.md: Update.

Florent Kermarrec · Oct 9, 2024, 2:42 PM UTC

dc3364a3c7ae

Merge pull request #2095 from trabucayre/zynqmp_ethernet_sgmii

enjoy-digital · Oct 9, 2024, 2:38 PM UTC

01c7a78f6716

soc/cores/cpu/zynqmp/core.py: added support for SGMII via PL with option PTP support

Gwenhael Goavec-Merou · Oct 9, 2024, 2:14 PM UTC

ddb8d16381da

Merge pull request #2093 from mgaggero/feature-alpine-linux

Gwenhael Goavec-Merou · Oct 9, 2024, 4:32 AM UTC

34b98ab578af

Fixes #2092: provides support for riscv gcc installation on Alpine Linux.

Massimo Gaggero · Oct 8, 2024, 6:46 PM UTC

e148650279c1

Merge pull request #2090 from VOGL-electronic/efinix_iobank

Gwenhael Goavec-Merou · Oct 8, 2024, 7:54 AM UTC

bc3e90c93a54

build: efinix: use ifacewriter to set bank voltage

Fin Maaß · Oct 8, 2024, 7:05 AM UTC

d26994916d3e

Merge pull request #2089 from VOGL-electronic/efinix_tristate_fix

enjoy-digital · Oct 7, 2024, 9:06 AM UTC

9ad5d2123129

build: efinix: Tristate fix

Fin Maaß · Oct 7, 2024, 8:15 AM UTC

4fcae9f3c72d

soc/integration/soc: Cleanup imports and directly use math.log2/ceil since math is already imported.

Florent Kermarrec · Oct 2, 2024, 3:08 PM UTC

64cf925b39b9

soc/intergration/soc/add_pcie: Add new status_width parameter.

Florent Kermarrec · Sep 27, 2024, 9:46 AM UTC

5e897752b79c

Merge pull request #2086 from VOGL-electronic/build_io_clocksignal

enjoy-digital · Oct 1, 2024, 9:49 AM UTC

644ef7e4e563

build: io: don't use mutable object as default value

Fin Maaß · Sep 30, 2024, 1:18 PM UTC

280b6b4ee4ca

CHANGES.md: Prepare for post 2024.08 changes.

Florent Kermarrec · Sep 27, 2024, 7:58 AM UTC

87ee6ec3a033

CHANGES.md: Do 2024.08 release.

Florent Kermarrec · Sep 27, 2024, 7:45 AM UTC

f72368abaa8e

setup.py: 2024.08 release.

Florent Kermarrec · Sep 27, 2024, 7:37 AM UTC

58e916d86ed8

CHANGES.md: Update.

Florent Kermarrec · Sep 27, 2024, 7:33 AM UTC

50bb6bb1ff03

build/efinix/efinity: Cosmetic cleanup on toolchain arguments.

Florent Kermarrec · Sep 26, 2024, 4:06 PM UTC

2130ff2fb354

build/efinix/common: Cosmetic cleanups.

Florent Kermarrec · Sep 26, 2024, 4:03 PM UTC

1568b25ff746

build/efinix/common: Enable back SDRInput since support fixed with recent changes.

Florent Kermarrec · Sep 26, 2024, 4:01 PM UTC

431feb0ac219

build/efinix/common: Switch to LiteXModule.

Florent Kermarrec · Sep 26, 2024, 3:46 PM UTC

9760493c32b4

Merge pull request #2083 from VOGL-electronic/efinix_common_improve

enjoy-digital · Sep 26, 2024, 3:41 PM UTC

95e5e7302ed4

Merge pull request #2079 from VOGL-electronic/efinix_iface_fixups

enjoy-digital · Sep 26, 2024, 3:31 PM UTC

c67dfa82cc90

build: efinix: EfinixTristateImpl: use GPIO Bus

Fin Maaß · Sep 26, 2024, 1:58 PM UTC

a825c61385eb

build: efinix: platform.py: add `get_pins_location` and `get_pins_name`

Fin Maaß · Sep 26, 2024, 1:53 PM UTC

e9a4b178ce65

build: efinix: use LiteXContext to get platform

Fin Maaß · Sep 26, 2024, 1:48 PM UTC

f8dc03810d18

efinix: common: replace `is_inclk_inverted`

Fin Maaß · Sep 25, 2024, 9:10 AM UTC

afcc477c4efc

efinix: ifacewriter: remove deprecated GPIO properties

Fin Maaß · Sep 25, 2024, 9:04 AM UTC

a605e758730d

efinix: ifacewriter: add `in_clk_inv` for GPIO INPUT block

Fin Maaß · Sep 25, 2024, 9:00 AM UTC

2c3536720cea

efinix: ifacewriter: fix `out_reg` in GPIO INOUT block

Fin Maaß · Sep 25, 2024, 8:59 AM UTC

10ab1b76c0fd

build/efinix/common: Disable SDRInput for now since breaking designs, needs to be investigated.

Florent Kermarrec · Sep 26, 2024, 10:58 AM UTC

b135f7151216

build/efinix/common: Update EfinixSDRInputImpl and minor cleanup.

Florent Kermarrec · Sep 26, 2024, 9:50 AM UTC

b5e91473b761

Merge pull request #2081 from VOGL-electronic/build_efinix_add_sdr_input

enjoy-digital · Sep 26, 2024, 9:43 AM UTC

0e337e20795c

Merge pull request #2078 from VOGL-electronic/efinix_add_ipm

enjoy-digital · Sep 26, 2024, 9:42 AM UTC

a19fbb70c4fd

Merge pull request #2082 from enjoy-digital/efinix_iface_signal_names

enjoy-digital · Sep 26, 2024, 9:42 AM UTC

b11cc8c3eb7f

build/efinix/common: Deprecate passing clk as str to avoid previous approach with pre-generated names.

Florent Kermarrec · Sep 26, 2024, 8:37 AM UTC

39d292a3c7b5

build/efinix/common: Directly pass ClockSignal/Signal to blocks and let the build resolve names.

Florent Kermarrec · Sep 26, 2024, 8:14 AM UTC

a3a55fc8fb30

build/efinix/efinity: Add resolve_iface_signal_names method to automatically resolve ClockSignal/Signal names passed in the blocks.

Florent Kermarrec · Sep 26, 2024, 8:12 AM UTC

fde9d2e4ad3c

build: efinix: common.py; add `SDRInput`

Fin Maaß · Sep 25, 2024, 3:17 PM UTC

61f715e6e77e

soc/cores/vexriscv_smp: Add the generation of the default sim config (https://github.com/litex-hub/linux-on-litex-vexriscv/issues/405)

Dolu1990 · Sep 25, 2024, 8:38 AM UTC

c3e87367c32c

build/sim/core/veril.cpp: Flush trace file on finish, fix issue with empty .fst dumps with short simulations.

Florent Kermarrec · Sep 25, 2024, 6:53 AM UTC

b86d76baed3e