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Commits included in published releases. Unpublished intermediate commits are private. Showing matches from the latest 100 commits ending at this release.

cores/video/VideoFramebuffer: Skip first frame on enable to ensure proper VTG/DMA synchronization.

Florent Kermarrec · Nov 5, 2023, 7:18 AM UTC

b0c0669ed362

cores/video: Fix missing h/vsync connection in SYNC state.

Florent Kermarrec · Nov 4, 2023, 7:55 PM UTC

f4e68d78ca84

Merge pull request #1824 from trabucayre/add_64_bus_support_v2

enjoy-digital · Oct 31, 2023, 8:17 PM UTC

71ae8fe82836

soc/interconnect/wishbone: InterconnectShared,Crossbar: using master adr_width for Interface constructor

Gwenhael Goavec-Merou · Oct 31, 2023, 10:59 AM UTC

755808e2872c

CHANGES: Update.

Florent Kermarrec · Oct 30, 2023, 6:40 PM UTC

9b8a5b6385b7

Merge pull request #1823 from trabucayre/cpuNone_config

enjoy-digital · Oct 30, 2023, 5:42 PM UTC

8c73afea9160

soc/integration/soc: fix typo at UARTBone call (addr_width -> address_width)

Gwenhael Goavec-Merou · Oct 30, 2023, 5:13 PM UTC

16133359d6ba

litex/soc/cores/cpu/init, litex/soc/integration/soc: modifying CPUNone to adapt data_width and io_regions according to bus data_width/address_width

Gwenhael Goavec-Merou · Oct 30, 2023, 4:17 PM UTC

eedebd8adb6f

Merge pull request #1822 from trabucayre/rework_tools

enjoy-digital · Oct 30, 2023, 4:13 PM UTC

4b9601bdab13

tools: litex_server, litex_client and remote: don't hardcode bus address

Gwenhael Goavec-Merou · Oct 30, 2023, 3:20 PM UTC

a2c39a7bbfc7

Merge pull request #1821 from trabucayre/uartbone_add_width

enjoy-digital · Oct 30, 2023, 2:03 PM UTC

5efdbd9c2015

soc/integration/soc: pass bus.address_width to UARTBone constructor

Gwenhael Goavec-Merou · Oct 30, 2023, 10:14 AM UTC

321254cc389b

soc/cores/uart: adding address_width (default 32bits) to UARTBone constructor

Gwenhael Goavec-Merou · Oct 30, 2023, 10:13 AM UTC

f06ef5205a8c

soc/cores/uart: allows 64bits in Stream2Wishbone

Gwenhael Goavec-Merou · Oct 30, 2023, 10:03 AM UTC

937419697427

cores/video: Simplify VTG/DMA synchronization and re-synchronize on each end of frame.

Florent Kermarrec · Oct 27, 2023, 4:07 PM UTC

b5a9106f56ab

Merge pull request #1818 from Dolu1990/nax-smp

enjoy-digital · Oct 27, 2023, 2:32 PM UTC

5842ad7d1449

core/naxriscv switch to main branch, and implement a reset controller internaly

Dolu1990 · Oct 27, 2023, 2:06 PM UTC

5e482d641c18

interconnect/wishbone: Revert SRAM to Module, needs to be investigated.

Florent Kermarrec · Oct 27, 2023, 1:24 PM UTC

d021564fca8a

Merge pull request #1816 from motec-research/test_csr_status_issue

enjoy-digital · Oct 27, 2023, 10:52 AM UTC

ff271b0b5f72

interconnect/stream: Revert Convert to Module, needs to be investigated.

Florent Kermarrec · Oct 27, 2023, 10:33 AM UTC

c44b906d9fcc

gen/fhdl/module: Ensure Module/Special/ClockDomains are initialized before adding them as submodules/specials/clock_domains.

Florent Kermarrec · Oct 27, 2023, 10:26 AM UTC

856d7452b317

CHANGES: Update.

Florent Kermarrec · Oct 27, 2023, 9:40 AM UTC

fa629b782f5d

Merge pull request #1804 from zeldin/ecp5_pll_phase

enjoy-digital · Oct 27, 2023, 9:37 AM UTC

e55cf0f6d982

soc/cores: Minor cosmetic changes.

Florent Kermarrec · Oct 27, 2023, 9:29 AM UTC

63159aa187a8

soc/cores: Make sure all Modules are switched to LiteXModule.

Florent Kermarrec · Oct 27, 2023, 9:16 AM UTC

48f27707d1fe

interconnect/packet: Switch to LiteXModule.

Florent Kermarrec · Oct 27, 2023, 9:07 AM UTC

a2820cba9633

interconnect/wishbone: Switch to LiteXModule.

Florent Kermarrec · Oct 27, 2023, 9:05 AM UTC

fa521f5c89f6

interconnect/stream: Switch to LiteXModule.

Florent Kermarrec · Oct 27, 2023, 9:03 AM UTC

9ccac7f7e0d4

soc/test: Make data_width/address_width/addressing explicit on Wishbone.Interface calls.

Florent Kermarrec · Oct 27, 2023, 8:55 AM UTC

002aad7a43c0

Merge pull request #1817 from enjoy-digital/wishbone_word_byte_addressing

enjoy-digital · Oct 27, 2023, 8:12 AM UTC

cd3265b16cd4

test_csr: test cases for issue

Andrew Dennison · Oct 27, 2023, 2:05 AM UTC

203726bc03bd

cores/cpu: Switch Wishbone interfaces to byte addressing where possible and remove address shifting.

Florent Kermarrec · Oct 26, 2023, 3:50 PM UTC

6e928efe8287

cores/cpu: Make data_width/address_width/addressing explicit for all Wishbone interfaces.

Florent Kermarrec · Oct 26, 2023, 3:40 PM UTC

75752b4bff01

soc/add_adapter: Add initial addressing conversion between byte/word addressed.

Florent Kermarrec · Oct 26, 2023, 3:25 PM UTC

7dc11e586b97

axi/axi_lite_to_wishbone: Add different address shift when Wishbone is byte/word addressed.

Florent Kermarrec · Oct 26, 2023, 3:24 PM UTC

b19b7ed0010f

csr_bus: Add addressing property.

Florent Kermarrec · Oct 26, 2023, 3:23 PM UTC

dde9605a5d03

ahb: Add addressing property and different address shift in AHB2Wishbone when Wishbone is byte/word addressed.

Florent Kermarrec · Oct 26, 2023, 3:23 PM UTC

c5d869447a7f

axi/axi_lite: Add addressing parameters and assert on byte.

Florent Kermarrec · Oct 26, 2023, 3:18 PM UTC

4524262f64e5

axi/axi_full: Add addressing parameters and assert on byte.

Florent Kermarrec · Oct 26, 2023, 3:18 PM UTC

d6f7652b68ba

interconnect/wishbone: Add addressing parameter/property to allow Wishbone to use byte addressing (Currently using word addressing).

Florent Kermarrec · Oct 26, 2023, 3:16 PM UTC

a4539c3dae2a

Merge pull request #1812 from trabucayre/efinix_ti60f100_spiflash

enjoy-digital · Oct 25, 2023, 3:47 PM UTC

7006b49a39c0

build/efinix/ifacewriter: adding internal Ti60F100 SPI Flash support

Gwenhael Goavec-Merou · Oct 12, 2023, 3:34 PM UTC

ba2913f13778

CHANGES: Update.

Florent Kermarrec · Oct 25, 2023, 2:01 PM UTC

69dc66617758

Merge pull request #1808 from hansfbaier/master

enjoy-digital · Oct 24, 2023, 6:41 AM UTC

cdeb4412f861

openxc7 toolchain: auto generate chipdb, if missing

Hans Baier · Oct 24, 2023, 5:01 AM UTC

f3f46e8cf10c

fix syntax errors

Hans Baier · Oct 24, 2023, 1:49 AM UTC

8d0f08a57e66

xilinx platform: add more ignored constraints for yosys+nextpnr

Hans Baier · Oct 24, 2023, 1:39 AM UTC

468375b11971

Merge pull request #1810 from trabucayre/etherbone_expose_params

enjoy-digital · Oct 23, 2023, 4:41 PM UTC

02b16f1f26cf

soc/integration/soc: expose interface and endianness to target (required for hybrid etherbone)

Gwenhael Goavec-Merou · Oct 23, 2023, 4:31 PM UTC

bf3286f564d9

build/generic_platform: Fix jtag_support typo.

Florent Kermarrec · Oct 23, 2023, 3:29 PM UTC

5a217528a46e

soc/build: Minimize changes added by #1809 and review.

Florent Kermarrec · Oct 23, 2023, 2:41 PM UTC

86cf24023d1c

Merge pull request #1809 from trabucayre/jtagbone_uartbone_parser

enjoy-digital · Oct 23, 2023, 2:03 PM UTC

ad98c7c630f5

soc/integration/soc_core: add new parameters --with-uartbone and --with-jtagbone, deprecate crossover+uartbone

Gwenhael Goavec-Merou · Oct 19, 2023, 3:52 PM UTC

745e584c60ab

Xilinx: Initial openxc7 toolchain support

Hans Baier · Oct 23, 2023, 4:38 AM UTC

a833193cd3eb

cores/clocks/lattice_ecp5: Fix phase calculation to match Diamond output

Marcus Comstedt · Jul 13, 2022, 9:12 AM UTC

6636560c41c9

build/openocd: adding Efinix Titanium support

Gwenhael Goavec-Merou · Oct 17, 2023, 3:37 PM UTC

7e6418900abc

soc/cores/jtag: adding Efinix JTAG support in JTAGPHY

Gwenhael Goavec-Merou · Oct 17, 2023, 3:37 PM UTC

aad83112601f

build/efinix/ifacewriter, soc/cores/ram/efinix_hyperram: adding F100 internal HyperRAM support

Gwenhael Goavec-Merou · Oct 17, 2023, 11:19 AM UTC

d95d5bdce977

build/efinix/ifacewriter: adding PHASE_SHIFT_xx and CLKOUTx_DYNPHASE_EN

Gwenhael Goavec-Merou · Oct 17, 2023, 11:17 AM UTC

6f02a7f5086a

soc/cores/clock/efinix: allows dyn_phase_shift configuration

Gwenhael Goavec-Merou · Oct 17, 2023, 11:17 AM UTC

cd439da18ece

build/efinix/dbparser: workaround for Ti60F100S3F2 with only 3 PLLs

Gwenhael Goavec-Merou · Oct 17, 2023, 11:17 AM UTC

5d7e9c94a6f1

build/openfpgaloader: Add unprotect_flash capability.

Florent Kermarrec · Oct 13, 2023, 11:14 AM UTC

e499dd84b5dc

build/openfpgaloader/flash: Add verify capability.

Florent Kermarrec · Oct 13, 2023, 7:26 AM UTC

fac003bbf9e7

core/naxriscv fix l2 parameters

Dolu1990 · Oct 12, 2023, 1:15 PM UTC

12f87212e385

Merge pull request #1800 from Dolu1990/nax-smp

Dolu1990 · Oct 12, 2023, 12:35 PM UTC

16fcfb9d7e79

core/naxriscv update

Dolu1990 · Oct 12, 2023, 11:44 AM UTC

0c77eb242d07

core/naxriscv update

Dolu1990 · Oct 12, 2023, 10:29 AM UTC

45b0c8dcd34e

Merge remote-tracking branch 'origin/master' into nax-smp

Dolu1990 · Oct 12, 2023, 7:20 AM UTC

bd9a37fd1cec

core/naxriscv now has an coherent l2 cache

Dolu1990 · Oct 12, 2023, 7:20 AM UTC

124ce5491856

CHANGES.md: Update.

Florent Kermarrec · Oct 11, 2023, 8:17 AM UTC

e426e78e312d

Merge pull request #1795 from zeldin/wb_downconverter_cti

enjoy-digital · Oct 11, 2023, 8:13 AM UTC

0ac75588af37

CHANGES: Update.

Florent Kermarrec · Oct 11, 2023, 7:13 AM UTC

0890bf4c1f4b

interconnect/wishbone: Add linear burst support to DownConverter

Marcus Comstedt · Oct 7, 2023, 7:25 AM UTC

196b68e4afdb

CHANGES: Update.

Florent Kermarrec · Oct 6, 2023, 5:50 PM UTC

5380df3994be

soc/cores/video/VideoFramebuffer: Add VTG/DMA synchronization when DMA is enabled to simplify use.

Florent Kermarrec · Oct 6, 2023, 8:10 AM UTC

cd8218779e0e

CHANGES: Update.

Florent Kermarrec · Oct 5, 2023, 6:25 AM UTC

98eb27df5265

Merge pull request #1627 from trabucayre/CC_PLL

enjoy-digital · Oct 5, 2023, 6:16 AM UTC

2d1072bd6727

Merge pull request #1617 from trabucayre/colognechip

enjoy-digital · Oct 5, 2023, 6:16 AM UTC

ffc38c0e7c67

build: adding colognechip toolchain

Gwenhael Goavec-Merou · Jun 13, 2022, 7:24 PM UTC

1370f503e840

soc/cores/clock: adding CologneChip CC_PLL

Gwenhael Goavec-Merou · Mar 1, 2023, 7:28 AM UTC

5fd5195a7dfb

build/xilinx/vivado: Add pre_optimize_commands.

Florent Kermarrec · Oct 3, 2023, 3:24 PM UTC

c0d376659669

build/efinix/common: adding Trion support for DifferentialOutput/DifferentialInput

Gwenhael Goavec-Merou · Oct 3, 2023, 5:00 AM UTC

ca43b00337bc

build/efinix/ifacewriter: fixed generate_lvds to support trion family

Gwenhael Goavec-Merou · Oct 3, 2023, 4:56 AM UTC

be655f556ac6

build/efinix/common: DifferentialInput support

Gwenhael Goavec-Merou · Oct 2, 2023, 3:32 PM UTC

728afdd7589c

build/efinix/ifacewriter: fix LVDS_TX, complete LVDS_RX

Gwenhael Goavec-Merou · Oct 2, 2023, 3:32 PM UTC

73a28d2c0458

build/efinix/common: adding DifferentialOutput support

Gwenhael Goavec-Merou · Oct 2, 2023, 12:56 PM UTC

97c84ebf274e

build/efinix/ifacewriter: adding method to generate lvds python code

Gwenhael Goavec-Merou · Oct 2, 2023, 12:53 PM UTC

cd1bd73a87fb

build/efinix/platform: adding method to get resource name based on signal

Gwenhael Goavec-Merou · Oct 2, 2023, 12:45 PM UTC

9842c95ef5b8

Merge pull request #1786 from motec-research/json2renode

AndrewD · Sep 30, 2023, 2:41 AM UTC

e8689eb1dc38

CHANGES: Update.

Florent Kermarrec · Sep 26, 2023, 11:49 AM UTC

f5b7c0d88e27

Merge pull request #1789 from protech-engineering/protech

enjoy-digital · Sep 26, 2023, 11:45 AM UTC

eda2221a784b

Update NEORV32 to verion 1.8.9

Matteo Marzaro · Sep 25, 2023, 10:07 AM UTC

a0f4c3715da2

litex_json2renode: fix --bios-binary and add --opensbi-binary

Andrew Dennison · Sep 25, 2023, 9:34 AM UTC

564f96c6c7c0

core/vexriscv_smp add --hardware-breakpoints INT to allow hardware breakpoint on PC

Dolu1990 · Sep 20, 2023, 7:10 AM UTC

3d956af81dab

Merge pull request #1782 from enjoy-digital/ci-dev-test

enjoy-digital · Sep 18, 2023, 8:02 AM UTC

7d7387374179

litex_setup: Don't do repo init in dev_mode (SSH clone) if running on CI.

Florent Kermarrec · Sep 18, 2023, 7:20 AM UTC

e0be02875375

CHANGES: Update.

Florent Kermarrec · Sep 18, 2023, 7:09 AM UTC

04a33c5ddb78

Merge pull request #1776 from Dolu1990/nax-smp

enjoy-digital · Sep 18, 2023, 7:05 AM UTC

4639c7b39c76

CHANGES.md: Start listing changes since 2023.08.

Florent Kermarrec · Sep 18, 2023, 6:56 AM UTC

8bd548d453e3

README: Update sponsors.

Florent Kermarrec · Sep 18, 2023, 6:55 AM UTC

46d9d8c780d1

Commit history

cores/video/VideoFramebuffer: Skip first frame on enable to ensure proper VTG/DMA synchronization.

cores/video: Fix missing h/vsync connection in SYNC state.

Merge pull request #1824 from trabucayre/add_64_bus_support_v2

soc/interconnect/wishbone: InterconnectShared,Crossbar: using master adr_width for Interface constructor

CHANGES: Update.

Merge pull request #1823 from trabucayre/cpuNone_config

soc/integration/soc: fix typo at UARTBone call (addr_width -> address_width)

litex/soc/cores/cpu/__init__, litex/soc/integration/soc: modifying CPUNone to adapt data_width and io_regions according to bus data_width/address_width

Merge pull request #1822 from trabucayre/rework_tools

tools: litex_server, litex_client and remote: don't hardcode bus address

Merge pull request #1821 from trabucayre/uartbone_add_width

soc/integration/soc: pass bus.address_width to UARTBone constructor

soc/cores/uart: adding address_width (default 32bits) to UARTBone constructor

soc/cores/uart: allows 64bits in Stream2Wishbone

cores/video: Simplify VTG/DMA synchronization and re-synchronize on each end of frame.

Merge pull request #1818 from Dolu1990/nax-smp

core/naxriscv switch to main branch, and implement a reset controller internaly

interconnect/wishbone: Revert SRAM to Module, needs to be investigated.

Merge pull request #1816 from motec-research/test_csr_status_issue

interconnect/stream: Revert Convert to Module, needs to be investigated.

gen/fhdl/module: Ensure Module/Special/ClockDomains are initialized before adding them as submodules/specials/clock_domains.

CHANGES: Update.

Merge pull request #1804 from zeldin/ecp5_pll_phase

soc/cores: Minor cosmetic changes.

soc/cores: Make sure all Modules are switched to LiteXModule.

interconnect/packet: Switch to LiteXModule.

interconnect/wishbone: Switch to LiteXModule.

interconnect/stream: Switch to LiteXModule.

soc/test: Make data_width/address_width/addressing explicit on Wishbone.Interface calls.

Merge pull request #1817 from enjoy-digital/wishbone_word_byte_addressing

test_csr: test cases for issue

cores/cpu: Switch Wishbone interfaces to byte addressing where possible and remove address shifting.

cores/cpu: Make data_width/address_width/addressing explicit for all Wishbone interfaces.

soc/add_adapter: Add initial addressing conversion between byte/word addressed.

axi/axi_lite_to_wishbone: Add different address shift when Wishbone is byte/word addressed.

csr_bus: Add addressing property.

ahb: Add addressing property and different address shift in AHB2Wishbone when Wishbone is byte/word addressed.

axi/axi_lite: Add addressing parameters and assert on byte.

axi/axi_full: Add addressing parameters and assert on byte.

interconnect/wishbone: Add addressing parameter/property to allow Wishbone to use byte addressing (Currently using word addressing).

Merge pull request #1812 from trabucayre/efinix_ti60f100_spiflash

build/efinix/ifacewriter: adding internal Ti60F100 SPI Flash support

CHANGES: Update.

Merge pull request #1808 from hansfbaier/master

openxc7 toolchain: auto generate chipdb, if missing

fix syntax errors

xilinx platform: add more ignored constraints for yosys+nextpnr

Merge pull request #1810 from trabucayre/etherbone_expose_params

soc/integration/soc: expose interface and endianness to target (required for hybrid etherbone)

build/generic_platform: Fix jtag_support typo.

soc/build: Minimize changes added by #1809 and review.

Merge pull request #1809 from trabucayre/jtagbone_uartbone_parser

soc/integration/soc_core: add new parameters --with-uartbone and --with-jtagbone, deprecate crossover+uartbone

Xilinx: Initial openxc7 toolchain support

cores/clocks/lattice_ecp5: Fix phase calculation to match Diamond output

build/openocd: adding Efinix Titanium support

soc/cores/jtag: adding Efinix JTAG support in JTAGPHY

build/efinix/ifacewriter, soc/cores/ram/efinix_hyperram: adding F100 internal HyperRAM support

build/efinix/ifacewriter: adding PHASE_SHIFT_xx and CLKOUTx_DYNPHASE_EN

soc/cores/clock/efinix: allows dyn_phase_shift configuration

build/efinix/dbparser: workaround for Ti60F100S3F2 with only 3 PLLs

build/openfpgaloader: Add unprotect_flash capability.

build/openfpgaloader/flash: Add verify capability.

core/naxriscv fix l2 parameters

Merge pull request #1800 from Dolu1990/nax-smp

core/naxriscv update

core/naxriscv update

Merge remote-tracking branch 'origin/master' into nax-smp

core/naxriscv now has an coherent l2 cache

CHANGES.md: Update.

Merge pull request #1795 from zeldin/wb_downconverter_cti

CHANGES: Update.

interconnect/wishbone: Add linear burst support to DownConverter

CHANGES: Update.

soc/cores/video/VideoFramebuffer: Add VTG/DMA synchronization when DMA is enabled to simplify use.

CHANGES: Update.

Merge pull request #1627 from trabucayre/CC_PLL

Merge pull request #1617 from trabucayre/colognechip

build: adding colognechip toolchain

litex/soc/cores/cpu/init, litex/soc/integration/soc: modifying CPUNone to adapt data_width and io_regions according to bus data_width/address_width