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Commits included in published releases. Unpublished intermediate commits are private. Showing matches from the latest 100 commits ending at this release.

test/test_hyperbus: Update.

Florent Kermarrec · Aug 21, 2024, 3:10 PM UTC

a88cee70c808

soc/cores/hyperbus: Simplify Clk Generation.

Florent Kermarrec · Aug 21, 2024, 3:10 PM UTC

37823e34b669

soc/core/hyperbus: Report Clk Ratio on Status register and use it in software to configure latency.

Florent Kermarrec · Aug 21, 2024, 1:35 PM UTC

ecd9eee5a4da

test/test_hyperbus: Add 2:1 test.

Florent Kermarrec · Aug 21, 2024, 1:00 PM UTC

5587f5954de2

soc/cores/hyperbus: Handle 4:1/2:1 specific cases separately, default to 4:1 mode (as before).

Florent Kermarrec · Aug 21, 2024, 10:07 AM UTC

d22669cf0532

soc/cores/hyperbus: Add cd_io/sync_io.

Florent Kermarrec · Aug 21, 2024, 9:50 AM UTC

f6de6e755efc

soc/cores/hyperbus: Add clk_ratio support to support x1/x2.

Florent Kermarrec · Aug 21, 2024, 9:41 AM UTC

43879b0f7351

soc/cores/hyperbus: WiP to make increase similarities between x1/x2 versions.

Florent Kermarrec · Aug 21, 2024, 9:17 AM UTC

22afa34a6453

soc/cores/hyperbus: Do some tests with sys_2x, seems working.

Florent Kermarrec · Aug 21, 2024, 8:57 AM UTC

50f0a1057c46

soc/cores/hyperbus: Add comment to allow switching to SDRTristate.

Florent Kermarrec · Aug 20, 2024, 8:05 PM UTC

0b028d395656

soc/cores/hyperbus: Avoid dq_oe condition to generate dq_o (was only useful for sim but now avoided).

Florent Kermarrec · Aug 20, 2024, 7:54 PM UTC

60f83b71fa5f

Merge pull request #2045 from enjoy-digital/hyperbus_io_regs

enjoy-digital · Aug 20, 2024, 5:47 PM UTC

298a004f08ae

software/libbase/hyperram: Add missing #ifdef.

Florent Kermarrec · Aug 20, 2024, 3:11 PM UTC

3a37d3ba98ae

soc/cores/hyperbus: Simplify CS and make it synchronous to allow IO Reg.

Florent Kermarrec · Aug 20, 2024, 2:19 PM UTC

eb29b40e077f

soc/cores/hyperbus: Make DQ/RWDS input sync explicit to allow IO Reg.

Florent Kermarrec · Aug 20, 2024, 1:44 PM UTC

1998c7454977

soc/cores/hyperbus: Make Rst synchronous to allow IO Reg (even if low speed).

Florent Kermarrec · Aug 20, 2024, 1:26 PM UTC

8b86b16077c5

test/test_hyperbus: Update.

Florent Kermarrec · Aug 20, 2024, 1:17 PM UTC

76cf0049132f

soc/software/libbase: Move HyperRAM init code to libbase/hyperram.c.

Florent Kermarrec · Aug 20, 2024, 12:58 PM UTC

b0026937c1c4

soc/cores/hyperbus: Avoid waiting for clk_phase in IDLE state to reduce latency.

Florent Kermarrec · Aug 20, 2024, 12:44 PM UTC

a30651e44e87

Merge pull request #2044 from VOGL-electronic/json2dts_zephyr_omit_disabled_handler

enjoy-digital · Aug 20, 2024, 12:29 PM UTC

b7605bc633f6

soc/cores/hyperbus: Rework Clk generation to allow having using an IO Reg.

Florent Kermarrec · Aug 20, 2024, 12:25 PM UTC

bfe000150c34

soc/cores/hyperbus: Directly specify default sys_clk_freq in init.

Florent Kermarrec · Aug 20, 2024, 10:04 AM UTC

7b413352c20f

soc/cores/hyperbus: Fix build with SDRTristate (to prepare tests with it).

Florent Kermarrec · Aug 20, 2024, 10:03 AM UTC

8f5c2dfbca17

soc/cores/hyperbus: Simplify/Rework Data Shift-Out Register.

Florent Kermarrec · Aug 20, 2024, 9:34 AM UTC

3a53a92bb2f1

soc/cores/hyperbus: Simplify/Rework Data Shift-In Register.

Florent Kermarrec · Aug 20, 2024, 9:26 AM UTC

9c1958d69219

json2dts_zephyr: omit disable handler

Fin Maaß · Aug 20, 2024, 9:13 AM UTC

c1403db40747

soc/cores/hyperbus: Better split parameters/signals and use intermediate dq_o/oe/i and rwds_o/oe/i signals.

Florent Kermarrec · Aug 20, 2024, 9:12 AM UTC

db86ec08b8bb

soc/cores/hyperbus: Cleanup CSn/Clk generation and add comments.

Florent Kermarrec · Aug 20, 2024, 8:40 AM UTC

1f71f3d68b5f

soc/cores/hyperbus: Minor cleanup changes.

Florent Kermarrec · Aug 20, 2024, 8:26 AM UTC

a960dc33bceb

soc/cores/hyperbus: Switch to Tristate instead of TSTriple and prepare for SDRTristate (not enabled for now).

Florent Kermarrec · Aug 20, 2024, 8:10 AM UTC

b95b66b55478

cores/picorv32: Fix idbus.sel for reads.

Florent Kermarrec · Aug 19, 2024, 11:34 AM UTC

afc66fd5cfd0

CHANGES.md: Update.

Florent Kermarrec · Aug 19, 2024, 8:37 AM UTC

bccd1e9c54c8

Merge pull request #2028 from VOGL-electronic/spi_ram_add

Gwenhael Goavec-Merou · Aug 16, 2024, 5:08 PM UTC

6623a5b691f3

Merge pull request #2042 from pepijndevos/apicula

Gwenhael Goavec-Merou · Aug 16, 2024, 4:58 PM UTC

26e7eef3ced6

add dual use gpio options

Pepijn de Vos · Aug 16, 2024, 1:56 PM UTC

039be2a248fb

Merge pull request #2036 from Mai-Lapyst/gowin-add-apicula

Gwenhael Goavec-Merou · Aug 15, 2024, 6:54 AM UTC

cbb1adfa7b15

Add missing license header to apicula.py

Mai-Lapyst · Aug 14, 2024, 11:54 PM UTC

dc3f2d642173

Remove empty build_timing_constraints override in GowinApiculaToolchain

Mai-Lapyst · Aug 14, 2024, 11:52 PM UTC

623536cd6af9

Adds apicula toolchain to gowin platform

Mai-Lapyst · Aug 12, 2024, 4:47 AM UTC

e0968b357442

Merge pull request #2035 from Mai-Lapyst/fix_empty_initpy

Gwenhael Goavec-Merou · Aug 11, 2024, 8:06 AM UTC

b279fc9fb318

Fix litex.build.gowin's init.py; closes #2034

Mai-Lapyst · Aug 11, 2024, 1:37 AM UTC

3d0fe4ebca0e

Merge pull request #2030 from trabucayre/gowin_build_gw5a_primitives

enjoy-digital · Aug 7, 2024, 7:23 AM UTC

6309f30e0b3f

build/gowin/common.py: re-add tristate impl and SDRxxx for GW5A/Arora family (required for SDRAM use)

Gwenhael Goavec-Merou · Aug 4, 2024, 7:38 AM UTC

3cd820974ab9

soc: add l2 cache to spi_ram

Fin Maaß · Jul 2, 2024, 8:50 AM UTC

cd457c98092b

openocd/jtagspi: Allow users to specify additional init commands

Matthias Breithaupt · Jun 5, 2024, 8:44 AM UTC

e29dc39377a4

bios: mem_read: reduce number of reads on mapped registers (only supports 32-bit aligned addresses)

Matthias Breithaupt · Jun 4, 2024, 8:45 AM UTC

41b346d141d9

soc: add add_spi_ram function

Matthias Breithaupt · May 24, 2024, 11:57 AM UTC

03a0a6fd9bfa

README.md: Be more positive and shorter in moral precisions :).

Florent Kermarrec · Jul 31, 2024, 12:55 PM UTC

f855417afccf

Merge pull request #2024 from trabucayre/altera_agilex5_sdrtristate_special

enjoy-digital · Jul 30, 2024, 5:22 PM UTC

74127d51c5b8

build/altera/common.py: implement SDRTristate for Agilex5 family

Gwenhael Goavec-Merou · Jul 30, 2024, 2:32 PM UTC

1f6673c6ebcc

Merge pull request #2021 from trabucayre/altera_agilex5_ddr_special

enjoy-digital · Jul 26, 2024, 4:26 PM UTC

3041150773c2

global: Remove @trabucayre's tracers :)

Florent Kermarrec · Jul 26, 2024, 10:56 AM UTC

ba8830e6cda8

interconnect/packet/PacketFIFO: Fix payload_fifo.sink.valid.

Florent Kermarrec · Jul 26, 2024, 9:52 AM UTC

5c5bc82f2261

build/altera/common,platform: added ddrinput/ddrout primitives

Gwenhael Goavec-Merou · Jul 25, 2024, 12:11 PM UTC

dc04949d782f

soc/integration/soc/add_uart: Allow directly passing uart_pads.

Florent Kermarrec · Jul 22, 2024, 2:22 PM UTC

c51d22074f68

soc/cores/clock/lattice_nx.py: added clk contraints for OSCA output

Gwenhael Goavec-Merou · Jul 22, 2024, 1:11 PM UTC

b8cb6da2b99a

cores/ram/lattice_nx: Revert #1906 since not working with RAM combining multiple SP512K.

Florent Kermarrec · Jul 22, 2024, 12:24 PM UTC

ecd0f0e5486e

Merge pull request #2012 from machdyne/master

enjoy-digital · Jul 21, 2024, 7:34 AM UTC

4662b95f1669

Merge pull request #2018 from motec-research/add_i2c_master

enjoy-digital · Jul 21, 2024, 7:32 AM UTC

4301293b213b

test_i2c: whitespace cleanups

Andrew Dennison · Sep 4, 2023, 1:16 AM UTC

67e6614eb22b

test_i2c: add more commands

Radek Pesina · Aug 29, 2023, 11:58 PM UTC

643f3f9a93b7

soc/cores/i2c: rewrite state machine

Andrew Dennison · Aug 29, 2023, 7:31 AM UTC

f99658200eda

test_i2c: update to use improved _MockTristate

Andrew Dennison · Aug 28, 2023, 5:49 AM UTC

13811aeacbbe

test_i2c: improve and document _MockTristate*

Andrew Dennison · Aug 28, 2023, 5:40 AM UTC

b779933a5f59

soc/cores/i2c: change SDA 1 or 2 cycles earlier

Andrew Dennison · Aug 28, 2023, 4:26 AM UTC

dce152b348d1

soc/cores/i2c: convert to LiteXModule and name some components

Andrew Dennison · Aug 28, 2023, 2:57 AM UTC

e36946b2511a

soc/cores/i2c: only change SDA when SCL is stable

Andrew Dennison · Aug 25, 2023, 5:24 AM UTC

c867d5647b41

soc/cores/i2c: remove unnecessary code

Andrew Dennison · Aug 23, 2023, 10:49 PM UTC

aef6cb310384

test_i2c: allow unit test to run directly

Andrew Dennison · Aug 25, 2023, 5:25 AM UTC

64ccd6df1cd5

soc/cores/i2c: change ISR to rising edge of idle

Richard Tucker · Feb 10, 2023, 1:50 AM UTC

5504cc626fe0

soc/cores/i2c: fix CSR generation

Richard Tucker · Feb 10, 2023, 1:49 AM UTC

b8b6ecef7cdf

test_i2c: test reading config

Andrew Dennison · Jan 31, 2023, 11:53 PM UTC

90128756f9e5

soc/cores/i2c: add interrupt

Andrew Dennison · Jan 16, 2023, 11:58 PM UTC

ad37e17743ee

test_i2c: generate i2c.vcd

Andrew Dennison · Jan 13, 2023, 4:48 AM UTC

4ddab34714ca

soc/cores: adapt misoc i2c to litex

Andrew Dennison · Jan 13, 2023, 1:57 AM UTC

a079da922a09

soc/cores/i2c: import from misoc

Andrew Dennison · Jan 13, 2023, 2:37 AM UTC

9dc3eefb7dad

tools/litex_sim: Cleanup imports.

Florent Kermarrec · Jul 18, 2024, 10:16 AM UTC

a014c4f07c9e

Merge pull request #2017 from Dolu1990/vexiiriscv

Dolu1990 · Jul 18, 2024, 9:37 AM UTC

8a08d5ca1980

Fix VexiiRiscv

Dolu1990 · Jul 18, 2024, 9:32 AM UTC

cbe7413feefd

Merge pull request #2016 from Dolu1990/vexiiriscv

enjoy-digital · Jul 18, 2024, 9:27 AM UTC

1b9bdbdce4b9

Update VexiiRiscv

Dolu1990 · Jul 18, 2024, 9:26 AM UTC

f687425cb195

Merge pull request #2011 from Dolu1990/vexiiriscv

Dolu1990 · Jul 12, 2024, 3:29 PM UTC

473784581d5e

Update Nax/Vexii

Dolu1990 · Jul 12, 2024, 2:17 PM UTC

9fa1b4c123ab

soc/cores/video: Add additional color formats

inc · Jul 10, 2024, 1:21 PM UTC

aef5a2094ee0

Merge branch 'master' into vexiiriscv

Dolu1990 · Jul 10, 2024, 7:37 AM UTC

22ff3ac42d10

Update Nax/Vexii

Dolu1990 · Jul 10, 2024, 7:35 AM UTC

1267ba8ae6f2

interconnect/axi/axi_lite: Add bursting property even if always False.

Florent Kermarrec · Jul 9, 2024, 3:02 PM UTC

e4e9bd212551

Merge branch 'nax64_irq' into vexiiriscv

Dolu1990 · Jul 9, 2024, 1:18 PM UTC

372ab2527326

build/efinix: Add default parameter values and fix other typos.

Florent Kermarrec · Jul 9, 2024, 8:04 AM UTC

549d23e4f70d

build/efinix: Fix typos (thanks @AndrewD).

Florent Kermarrec · Jul 9, 2024, 8:00 AM UTC

e6171e79dbef

Merge pull request #2009 from trabucayre/efinix_args_opts

enjoy-digital · Jul 8, 2024, 3:01 PM UTC

7de4f01aa8bc

build/efinix: added argument to change synthesis options configurations

Gwenhael Goavec-Merou · Jul 8, 2024, 1:59 PM UTC

ec1528fb690e

soc/interconnect/stream: Improve MonitorCounter timings (avoid reset, clearer logic).

Florent Kermarrec · Jul 5, 2024, 11:55 AM UTC

0db650ac6a1e

cores/can/ctu_can_fd: Remove pads.irq that was used as debug.

Florent Kermarrec · Jul 5, 2024, 7:34 AM UTC

3c2ddd1655eb

Merge pull request #2007 from enjoy-digital/ctu-can-fd

enjoy-digital · Jul 5, 2024, 7:16 AM UTC

7ec35eb4c5f6

Merge pull request #2006 from trabucayre/update_altera_build

enjoy-digital · Jul 4, 2024, 11:04 AM UTC

d838a9ca737e

build/altera/quartus.py: added support for ips other than QSYS_FILE

Gwenhael Goavec-Merou · Jul 4, 2024, 7:51 AM UTC

9fd63973aa71

build/altera/platform,quartus: allows user to select Analysis&Synthesis tool (quartus_map (default) or quartus_syn

Gwenhael Goavec-Merou · Jul 4, 2024, 7:50 AM UTC

7393c35264f3

Merge pull request #2005 from VOGL-electronic/json2dts_zephyr_remove_configs

enjoy-digital · Jul 4, 2024, 7:10 AM UTC

b286fe5621da

gen/fhdl/hierarchy: Sort instances to generate deterministic hierarchy in verilog.

Florent Kermarrec · Jul 3, 2024, 7:44 PM UTC

d4d1a1bfd76b

Commit history

test/test_hyperbus: Update.

soc/cores/hyperbus: Simplify Clk Generation.

soc/core/hyperbus: Report Clk Ratio on Status register and use it in software to configure latency.

test/test_hyperbus: Add 2:1 test.

soc/cores/hyperbus: Handle 4:1/2:1 specific cases separately, default to 4:1 mode (as before).

soc/cores/hyperbus: Add cd_io/sync_io.

soc/cores/hyperbus: Add clk_ratio support to support x1/x2.

soc/cores/hyperbus: WiP to make increase similarities between x1/x2 versions.

soc/cores/hyperbus: Do some tests with sys_2x, seems working.

soc/cores/hyperbus: Add comment to allow switching to SDRTristate.

soc/cores/hyperbus: Avoid dq_oe condition to generate dq_o (was only useful for sim but now avoided).

Merge pull request #2045 from enjoy-digital/hyperbus_io_regs

software/libbase/hyperram: Add missing #ifdef.

soc/cores/hyperbus: Simplify CS and make it synchronous to allow IO Reg.

soc/cores/hyperbus: Make DQ/RWDS input sync explicit to allow IO Reg.

soc/cores/hyperbus: Make Rst synchronous to allow IO Reg (even if low speed).

test/test_hyperbus: Update.

soc/software/libbase: Move HyperRAM init code to libbase/hyperram.c.

soc/cores/hyperbus: Avoid waiting for clk_phase in IDLE state to reduce latency.

Merge pull request #2044 from VOGL-electronic/json2dts_zephyr_omit_disabled_handler

soc/cores/hyperbus: Rework Clk generation to allow having using an IO Reg.

soc/cores/hyperbus: Directly specify default sys_clk_freq in __init__.

soc/cores/hyperbus: Fix build with SDRTristate (to prepare tests with it).

soc/cores/hyperbus: Simplify/Rework Data Shift-Out Register.

soc/cores/hyperbus: Simplify/Rework Data Shift-In Register.

json2dts_zephyr: omit disable handler

soc/cores/hyperbus: Better split parameters/signals and use intermediate dq_o/oe/i and rwds_o/oe/i signals.

soc/cores/hyperbus: Cleanup CSn/Clk generation and add comments.

soc/cores/hyperbus: Minor cleanup changes.

soc/cores/hyperbus: Switch to Tristate instead of TSTriple and prepare for SDRTristate (not enabled for now).

cores/picorv32: Fix idbus.sel for reads.

CHANGES.md: Update.

Merge pull request #2028 from VOGL-electronic/spi_ram_add

Merge pull request #2042 from pepijndevos/apicula

add dual use gpio options

Merge pull request #2036 from Mai-Lapyst/gowin-add-apicula

Add missing license header to apicula.py

Remove empty build_timing_constraints override in GowinApiculaToolchain

Adds apicula toolchain to gowin platform

Merge pull request #2035 from Mai-Lapyst/fix_empty_initpy

Fix litex.build.gowin's __init__.py; closes #2034

Merge pull request #2030 from trabucayre/gowin_build_gw5a_primitives

build/gowin/common.py: re-add tristate impl and SDRxxx for GW5A/Arora family (required for SDRAM use)

soc: add l2 cache to spi_ram

openocd/jtagspi: Allow users to specify additional init commands

bios: mem_read: reduce number of reads on mapped registers (only supports 32-bit aligned addresses)

soc: add add_spi_ram function

README.md: Be more positive and shorter in moral precisions :).

Merge pull request #2024 from trabucayre/altera_agilex5_sdrtristate_special

build/altera/common.py: implement SDRTristate for Agilex5 family

Merge pull request #2021 from trabucayre/altera_agilex5_ddr_special

global: Remove @trabucayre's tracers :)

interconnect/packet/PacketFIFO: Fix payload_fifo.sink.valid.

build/altera/common,platform: added ddrinput/ddrout primitives

soc/integration/soc/add_uart: Allow directly passing uart_pads.

soc/cores/clock/lattice_nx.py: added clk contraints for OSCA output

cores/ram/lattice_nx: Revert #1906 since not working with RAM combining multiple SP512K.

Merge pull request #2012 from machdyne/master

Merge pull request #2018 from motec-research/add_i2c_master

test_i2c: whitespace cleanups

test_i2c: add more commands

soc/cores/i2c: rewrite state machine

test_i2c: update to use improved _MockTristate

test_i2c: improve and document _MockTristate*

soc/cores/i2c: change SDA 1 or 2 cycles earlier

soc/cores/i2c: convert to LiteXModule and name some components

soc/cores/i2c: only change SDA when SCL is stable

soc/cores/i2c: remove unnecessary code

test_i2c: allow unit test to run directly

soc/cores/i2c: change ISR to rising edge of idle

soc/cores/i2c: fix CSR generation

test_i2c: test reading config

soc/cores/i2c: add interrupt

test_i2c: generate i2c.vcd

soc/cores: adapt misoc i2c to litex

soc/cores/i2c: import from misoc

tools/litex_sim: Cleanup imports.

Merge pull request #2017 from Dolu1990/vexiiriscv

Fix VexiiRiscv

soc/cores/hyperbus: Directly specify default sys_clk_freq in init.

Fix litex.build.gowin's init.py; closes #2034