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Commits included in published releases. Unpublished intermediate commits are private. Showing matches from the latest 100 commits ending at this release.

cores/code_8b10b: Remove DecoderComb, avoids duplication for a 1 cycle gain that is probably not useful.

Florent Kermarrec · May 19, 2025, 9:25 AM UTC

af4f6eff5aca

soc: interconnect: csr_eventmanager: add trigger on any edge

Fin Maaß · Mar 13, 2025, 1:43 PM UTC

860a451312f7

cores: 8b10b: add combinatorial decoder

Fin Maaß · Feb 7, 2025, 1:44 PM UTC

20e1f49cd633

build: efinix: ifacewriter: lvds: make more things settable

Fin Maaß · Feb 7, 2025, 1:40 PM UTC

6661af24cd91

Merge pull request #2220 from maleadt/patch-1

enjoy-digital · Apr 1, 2025, 11:30 AM UTC

d70a3cf67dd9

OpenFPGALoader wrapper: add support for `reset` command

Tim Besard · Apr 1, 2025, 10:01 AM UTC

51b4acb1136c

Merge pull request #2198 from VOGL-electronic/json2dts_zephyr_eth

enjoy-digital · Mar 26, 2025, 6:28 PM UTC

e6c63abe2766

Merge pull request #2211 from mohammadshahidzade/master

enjoy-digital · Mar 26, 2025, 3:58 PM UTC

191c5d863c18

Merge pull request #2214 from gvillanovanm/fix-tftp-oack-handling

enjoy-digital · Mar 26, 2025, 3:53 PM UTC

fbf218f8fde7

Fix TFTP PUT: handle OACK properly by setting last_ack and data_port

Gabriel Villanova · Mar 24, 2025, 4:01 PM UTC

478851d535e3

Merge pull request #2210 from benjaminh-13/master

enjoy-digital · Mar 24, 2025, 7:48 AM UTC

b1eb23bec2ae

now we have both baremetal mode with no plic and linux mode with plic(it's more efficient ot not use plic in the baremetal case)

msa417 · Mar 21, 2025, 9:08 PM UTC

b27e7d349487

the test are complete going back to the original litex_setup wihtout modified paths

msa417 · Mar 21, 2025, 12:26 AM UTC

a6593beedbda

fixing the plic start address

msa417 · Mar 21, 2025, 12:11 AM UTC

1b39bebb84b7

cleaning the code and add the two options of axi and wishbone plus giving the option of changing the cpu count to the user coupled with giving the user the option to exclude the clint

msa417 · Mar 20, 2025, 11:59 PM UTC

47b97b087a16

forcing it to use the new repos

msa417 · Mar 20, 2025, 10:44 PM UTC

08f646880ec5

for got the /

msa417 · Mar 20, 2025, 10:34 PM UTC

8de543575f75

checkig if the cva5 fork works correclty

msa417 · Mar 20, 2025, 10:33 PM UTC

ecd9a213cbed

multicore CVA5 with linux support plus the plic and clint modules

msa417 · Mar 19, 2025, 11:08 PM UTC

c7ea510eca15

adding CVA5 isr into the isr.c

msa417 · Mar 19, 2025, 11:03 PM UTC

c1fbbbde4222

Fix enjoy-digital#2200

benjaminh-13 · Mar 18, 2025, 5:18 PM UTC

4218801596a7

Merge pull request #2206 from VOGL-electronic/uart_slice_data

enjoy-digital · Mar 17, 2025, 10:09 AM UTC

88258bd34795

Merge pull request #2203 from enjoy-digital/Dolu1990-patch-4

enjoy-digital · Mar 17, 2025, 8:10 AM UTC

469a07d0c208

Merge pull request #2205 from VOGL-electronic/bios_netboot_tftp

enjoy-digital · Mar 17, 2025, 8:08 AM UTC

b844dd20e1cb

cores: uart.py: slice data in fsm run

Fin Maaß · Feb 20, 2025, 2:09 PM UTC

f34aadc895ed

bios: tftp: add error message

Fin Maaß · Feb 20, 2025, 2:12 PM UTC

ebc10fdedea1

bios: add ETH_NETBOOT_SKIP_JSON

Fin Maaß · Feb 20, 2025, 2:07 PM UTC

76e194e6cc8f

cores/cpu/vexiiriscv : Fix #2202 long boot time

Dolu1990 · Mar 10, 2025, 1:38 PM UTC

92a64e42de84

tools: json2dts_zephyr: don't skip interrupt 0

Fin Maaß · Mar 7, 2025, 1:39 PM UTC

2a97b0308bf0

tools: json2dts_zephyr: add handler for ethphy mdio

Fin Maaß · Mar 6, 2025, 10:46 AM UTC

8381779322e7

Merge pull request #2197 from VOGL-electronic/efinix_topaz

Gwenhael Goavec-Merou · Mar 5, 2025, 3:49 PM UTC

48e65c199de6

build: efinix: add Topaz support

Fin Maaß · Mar 4, 2025, 3:51 PM UTC

a0159e18ad8c

tools: json2dts_zephyr: make generate_dts_config() reuseable

Fin Maaß · Mar 5, 2025, 9:46 AM UTC

778d39d5c1dc

tools: json2dts_zephyr: make the config overlay file optional

Fin Maaß · Mar 5, 2025, 9:44 AM UTC

dea051767d3e

tools: json2dts_zephyr: only add CSR_DATA_WIDTH, when on non default value

Fin Maaß · Mar 5, 2025, 9:42 AM UTC

cd8539876839

tools: json2dts_zephyr: add prbs0

Fin Maaß · Mar 5, 2025, 9:39 AM UTC

66447904a1d2

tools: json2dts_zephyr: split ethmac buffers

Fin Maaß · Mar 5, 2025, 9:37 AM UTC

f38b09dab2b4

soc/cores/clock/xilinx_commom: Add clk_domain paramrter to expose_dps method.

Florent Kermarrec · Mar 4, 2025, 2:36 PM UTC

904c3825f15c

Merge pull request #2193 from VOGL-electronic/efinix_programmer_flash

enjoy-digital · Mar 4, 2025, 1:37 PM UTC

a3a5fc5e91be

build: efinix: programmer: add flash function

Fin Maaß · Mar 3, 2025, 10:32 AM UTC

761184110bd4

soc/cores/clock/xilinx_common: Add expose_dps method to XilinxClocking to expose Dynamic Phase Shift interface of MMCMs.

Florent Kermarrec · Feb 28, 2025, 3:27 PM UTC

2c98fed25d51

soc/cores/clock: Add more separators between Xilinx modules.

Florent Kermarrec · Feb 28, 2025, 2:28 PM UTC

ef743595a484

Merge pull request #2189 from cr1901/minerva-up

enjoy-digital · Feb 20, 2025, 1:32 PM UTC

dd54d77db7a2

Merge pull request #2191 from VOGL-electronic/efinity-db-fix

enjoy-digital · Feb 20, 2025, 1:12 PM UTC

d9e62808d3fb

Fix Efinity 2024.2 missing device_*.xml files

Matthias Breithaupt · Feb 20, 2025, 12:15 PM UTC

f7cafba65599

Fix CSR register names for Minerva support code.

William D. Jones · Feb 19, 2025, 8:31 PM UTC

42b0c23a4db6

Bring Minerva up to date with upstream.

William D. Jones · Feb 19, 2025, 7:52 PM UTC

2f4f005e892b

soc/cores/identifier: Raise ValueError when comma is present in ident, otherwise breaking .csv support.

Florent Kermarrec · Feb 19, 2025, 8:02 AM UTC

495708530e2a

Merge pull request #2188 from cr1901/hier-cp1252

enjoy-digital · Feb 19, 2025, 7:52 AM UTC

ec9927b025c0

Merge pull request #2174 from cr1901/sentinel

enjoy-digital · Feb 18, 2025, 9:10 PM UTC

d54ed022a64f

Use CP1252-compatible chars for hierarchy on Windows.

William D. Jones · Feb 18, 2025, 6:11 PM UTC

98992098cc96

Add myself to copyrights of Sentinel Python files.

William D. Jones · Feb 18, 2025, 5:47 PM UTC

e48bb953c897

Merge pull request #2187 from benjaminh-13/master

enjoy-digital · Feb 18, 2025, 7:12 AM UTC

3f8b0bbd0679

Fix issue enjoy-digital#2182

benjaminh-13 · Feb 17, 2025, 3:09 PM UTC

b5b52b630a05

Improve private area decoding.

William D. Jones · Feb 8, 2025, 7:02 PM UTC

5feddf800438

Add support for the Sentinel RISC-V CPU.

William D. Jones · Feb 3, 2025, 1:09 AM UTC

a679dc4c6898

Merge pull request #2186 from higuoxing/escape

enjoy-digital · Feb 17, 2025, 10:26 AM UTC

994e422d1bf3

Merge pull request #2185 from cr1901/memspeed-opt

enjoy-digital · Feb 17, 2025, 10:25 AM UTC

0dfec738b991

Merge pull request #2181 from enjoy-digital/efinix_get_pins_name_multi_def

enjoy-digital · Feb 17, 2025, 10:20 AM UTC

c1c2edd3dd59

Merge pull request #2183 from tarik-hamedovic/master

enjoy-digital · Feb 17, 2025, 7:57 AM UTC

32afc5ee326a

Use Python's raw string in regex pattern.

Xing Guo · Feb 17, 2025, 1:34 AM UTC

5c5d116bc6b3

Optimize memspeed test for cores with slow modulo.

William D. Jones · Feb 16, 2025, 11:14 PM UTC

3b558ffd7bf3

Added fujprog in lattice progammer

TarikHamedovic · Feb 16, 2025, 12:13 AM UTC

5b28fb803c1e

build/efinix/platform.py: get_pins_name: avoids to create a new signal with a name already existing

Gwenhael Goavec-Merou · Feb 14, 2025, 9:11 AM UTC

cdbfa8b490ff

litex_setup.py: Add editable to GitRepo and set to to False for migen.

Florent Kermarrec · Feb 13, 2025, 4:55 PM UTC

bc1f1f52b020

Merge pull request #2176 from david-sawatzke/python_311_support

enjoy-digital · Feb 13, 2025, 4:42 PM UTC

adf77f34711a

Merge pull request #2180 from trabucayre/efinix_sdrinput

enjoy-digital · Feb 13, 2025, 4:42 PM UTC

3d500c861ce3

litex/build/efinix/platform.py: get_pin_name method: always adds idx to the signal name -> avoid some inversion between my_sig and my_sig_1

Gwenhael Goavec-Merou · Feb 13, 2025, 2:26 PM UTC

a3f9ef11b6ed

Update migen version to work with python3.11

David Sawatzke · Feb 5, 2025, 9:52 AM UTC

9d906726a891

Merge pull request #2171 from trabucayre/gw5at_plla

enjoy-digital · Feb 3, 2025, 7:25 PM UTC

2bcbbafdd679

soc/cores/clock/gowin_gw5a.py: GW5AT uses PLLA

Gwenhael Goavec-Merou · Feb 2, 2025, 3:25 PM UTC

f81e05e20b35

Merge pull request #2026 from VOGL-electronic/core_litei2c

enjoy-digital · Jan 28, 2025, 1:52 PM UTC

c213c42745ea

Merge pull request #2168 from VOGL-electronic/build_tristate_io

enjoy-digital · Jan 27, 2025, 7:54 AM UTC

03823f44e783

Merge pull request #2165 from VOGL-electronic/bring_back_lower_slice

enjoy-digital · Jan 27, 2025, 7:53 AM UTC

d07c068fcb99

build: common: TristateImpl: support longer oe

Fin Maaß · Jan 23, 2025, 12:34 PM UTC

913a7096269f

litex: gen: fhdl: verilog.py: resolve slice of Cat and Replicate

Fin Maaß · Jan 23, 2025, 12:22 PM UTC

0ba777f5ffb7

litex: gen: fhdl: verilog.py: resolve slice in lower_complex_slices()

Fin Maaß · Jan 20, 2025, 10:01 AM UTC

e989564369e9

Merge pull request #2167 from VOGL-electronic/fix_sinals_for_multibit_io

enjoy-digital · Jan 22, 2025, 2:04 PM UTC

ad5d7d343821

build: common: make sure Signal lenght is right

Fin Maaß · Jan 22, 2025, 10:13 AM UTC

a019fd4ed4f9

gen/fhdl: Revert PR #2161 since introducing regressions.

Florent Kermarrec · Jan 20, 2025, 9:46 AM UTC

666c9b430984

Merge pull request #2162 from trabucayre/altera_max10_fullmemorywe

enjoy-digital · Jan 16, 2025, 1:21 PM UTC

e9e7cd9f39e5

build/altera/quartus.py: don't call FullMemoryWE when target is based on max10 FPGA

Gwenhael Goavec-Merou · Jan 16, 2025, 1:08 PM UTC

08a8b666f8dd

CHANGES.md: Update.

Florent Kermarrec · Jan 15, 2025, 8:15 AM UTC

08a6da2140fd

Merge pull request #2161 from VOGL-electronic/expression_slice

enjoy-digital · Jan 15, 2025, 7:41 AM UTC

fefe3171c62c

Merge pull request #2160 from FlyGoat/ibex

enjoy-digital · Jan 15, 2025, 7:28 AM UTC

a9265ef7aa0d

gen: fhdl: expression: resolve slice completly

Fin Maaß · Jan 14, 2025, 6:40 PM UTC

29fc4715bba5

cores/cpu/ibex: Align with latest RTL

Jiaxun Yang · Jan 14, 2025, 5:58 PM UTC

c13cbd3b06d5

Merge pull request #2159 from FlyGoat/openc906-fixes

enjoy-digital · Jan 14, 2025, 5:10 PM UTC

5619d48f829a

litex/gen/fhdl/expression: Improve _generate_slice to avoid slicing all 1-bit Signals and cleanup.

Florent Kermarrec · Jan 14, 2025, 4:57 PM UTC

279b758584a6

litex/gen/fhdl/instance: Switch to expression.py.

Florent Kermarrec · Jan 14, 2025, 4:36 PM UTC

e71e404ef459

litex/gen/fhdl: Move expression generation function to expression.py.

Florent Kermarrec · Jan 14, 2025, 4:35 PM UTC

0bfaf39d579f

Merge pull request #2105 from VOGL-electronic/add_io_bus

enjoy-digital · Jan 14, 2025, 4:59 PM UTC

4933bcb6bf50

cores/cpu/openc906: Align with pythondata RTL

Jiaxun Yang · Jan 13, 2025, 5:27 PM UTC

ea3106877814

build: io: SDRIO/Tristate: check len after wrap

Fin Maaß · Nov 14, 2024, 9:31 AM UTC

e7a55fa73374

build: common: extend SDR/DDR

Fin Maaß · Nov 13, 2024, 3:22 PM UTC

410804c8b8ef

CHANGES.md: Switch formating to proper markdown for last release (for proper link support) and add release date.

Florent Kermarrec · Jan 7, 2025, 8:05 AM UTC

a1ea5a2f60c3

Merge pull request #2140 from piotro888/ethernet-full-mem-we-quartus

enjoy-digital · Jan 6, 2025, 9:03 PM UTC

c55086f62126

CHANGES.md: Update.

Florent Kermarrec · Jan 6, 2025, 8:59 PM UTC

74ea99ac039f

build/altera: apply FullMemoryWE for Quartus toolchain

Piotr Wegrzyn · Jan 6, 2025, 8:14 PM UTC

118bd62f0c11

tools/litex_client: Display size on Bytes/KB/MB/GB in Memory Regions.

Florent Kermarrec · Jan 6, 2025, 1:33 PM UTC

5c156b4999ba