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Commits included in published releases. Unpublished intermediate commits are private. Showing matches from the latest 100 commits ending at this release.

wishbone/cache: share lane selection across read fast paths

Florent Kermarrec · Sep 5, 2026, 6:53 AM UTC

6a60c5fa78fd

wishbone/cache: optionally forward read-miss refill responses

Florent Kermarrec · Sep 5, 2026, 6:37 AM UTC

68993b479611

wishbone/cache: add opt-in same-line read-burst fast path

Florent Kermarrec · Sep 5, 2026, 6:29 AM UTC

17407283e22f

bench: reject stale runs and fingerprint simulation builds

Florent Kermarrec · Sep 4, 2026, 9:34 PM UTC

eb7c45024967

litex_sim: expose SDRAM L2 refill width for performance tuning

Florent Kermarrec · Sep 4, 2026, 9:30 PM UTC

2761ac8eb002

bench: measure CPU and memory cycles with LiteX Sim

Florent Kermarrec · Sep 4, 2026, 9:28 PM UTC

3114322d9966

Merge pull request #2565 from enjoy-digital/software-custom-sdram-init

enjoy-digital · Sep 4, 2026, 12:08 PM UTC

cfb382f54f81

software: allow custom SDRAM initialization

Florent Kermarrec · Sep 4, 2026, 7:02 AM UTC

fb6c2a1c5ea8

Merge pull request #2564 from trabucayre/zynq7000_ps7-mio_support

enjoy-digital · Sep 3, 2026, 9:51 AM UTC

9b6b3838ba69

soc/cores/cpu/zynq7000/core.py: added MIO mode and pin configuration for add_can, add_uart, add_sdio, add_spi, add_i2c and add_ethernet

Gwenhael Goavec-Merou · Sep 3, 2026, 5:38 AM UTC

f3d8e44b6d5c

doc: update unreleased changelog

Florent Kermarrec · Sep 2, 2026, 1:30 PM UTC

86f29574801f

Merge pull request #2559 from rvodden/pr-setup-packaging

enjoy-digital · Sep 2, 2026, 6:55 AM UTC

dc965addb7d8

litex_setup: Install packaging>=24.2 alongside setuptools

Richard Vodden · Aug 27, 2026, 6:49 AM UTC

878c9c0a0949

Merge pull request #2561 from enjoy-digital/fix/axi-downconverter-narrow-serialization

enjoy-digital · Sep 2, 2026, 6:44 AM UTC

c07f3087a05c

soc/interconnect/axi: serialize narrow down-converter accesses

Florent Kermarrec · Sep 2, 2026, 6:38 AM UTC

60bc97ef76c4

cpu/veer_eh1: align integration with LiteX conventions

Florent Kermarrec · Sep 1, 2026, 12:36 PM UTC

9cd4b76753a6

Merge pull request #2556 from SilverLining-EDA/add-veer-eh1-cpu

Florent Kermarrec · Sep 1, 2026, 12:43 PM UTC

2b587e57f19a

cpu/vexiiriscv: implement flush_cpu_dcache() via Zicbom CBO sweep

Florent Kermarrec · Aug 28, 2026, 9:57 AM UTC

6c793c27f94a

litex_repos: point pythondata-cpu-veer_eh1 to litex-hub

Bilal Ali · Aug 27, 2026, 5:29 AM UTC

1b5af403da83

Merge pull request #2554 from shenki/cva6-fixes

enjoy-digital · Aug 25, 2026, 1:04 PM UTC

8bafc04e98d3

Merge pull request #2550 from hansfbaier/fix-hierarchical-memory-port-wire

enjoy-digital · Aug 25, 2026, 12:59 PM UTC

0d7ef3cd3ad5

Merge pull request #2553 from trabucayre/vhd2v_converter_fix_missing_params

enjoy-digital · Aug 25, 2026, 12:58 PM UTC

72d319be4470

Merge pull request #2552 from rvodden/pr-json2dts-i2c-buses

enjoy-digital · Aug 25, 2026, 12:57 PM UTC

84b9b65990aa

Merge pull request #2551 from blurbdust/stratixv-fixes

enjoy-digital · Aug 25, 2026, 12:56 PM UTC

b1542326a689

soc/software: wire up VeeR EH1 PIC interrupt init in isr.c

Bilal Ali · Aug 25, 2026, 10:58 AM UTC

f2709aba3973

cpu/veer_eh1: add VeeR EH1 CPU core support

Bilal Ali · Aug 25, 2026, 10:48 AM UTC

1333149d66f4

cpu/cva6: Export correct CLINT timebase

Joel Stanley · Aug 10, 2026, 5:55 AM UTC

b9cfc13a14f9

cpu/cva6: Export CPU_ISA, CPU_MMU and CLINT/PLIC regions for the DT

Joel Stanley · Aug 10, 2026, 5:54 AM UTC

6179d7425760

cpu/cva6: Mark the LiteX IO region (0x80000000+) non-idempotent

Joel Stanley · Aug 10, 2026, 5:53 AM UTC

703b782a777b

cpu/cva6: Move csr base to 0xf0000000 to avoid ethmac IO overlap

Joel Stanley · Aug 10, 2026, 5:52 AM UTC

055a80a95165

cpu/cva6: Cut AXI channels between atomics adapter and LiteX bus

Joel Stanley · Aug 10, 2026, 5:51 AM UTC

53458999d53c

cpu/cva6: Resolve AMOs/LR-SC in front of the LiteX bus

Joel Stanley · Aug 10, 2026, 5:51 AM UTC

c7205711e0b2

cpu/cva6: Map LiteX interrupt line to same numbered PLIC source

Joel Stanley · Aug 15, 2026, 12:59 PM UTC

96724ca4eee4

cpu/cva6: Fix PLIC NumSources mismatch

Joel Stanley · Aug 10, 2026, 5:49 AM UTC

a2e31cbde6c4

build/vhd2v_converter.py: when vhd files are not converted to verilog: keep p_xxx params in ip_params. Otherwise build may fails

Gwenhael Goavec-Merou · Aug 17, 2026, 11:02 AM UTC

6fc30900ad7f

build/vhd2v_converter.py: updates extract_prefixed_generics to pass target to extract_prefixed_generics (default value: GHDL)

Gwenhael Goavec-Merou · Aug 17, 2026, 11:01 AM UTC

bf8f72696541

build/converter_common.py: added target argument in extract_prefixed_generics to return a dict p_xxx: val when target is not GHDL

Gwenhael Goavec-Merou · Aug 17, 2026, 11:00 AM UTC

5426cd6f4c46

tools/json2dts: emit a node for every I2C bus, not just i2c0

Richard Vodden · Aug 15, 2026, 9:45 AM UTC

96dd8760074e

build/openocd: add StratixV IR (0xe) to get_ir

blurbdust · Aug 14, 2026, 8:33 PM UTC

a772000d7514

litex/gen: fix hierarchical Verilog wire classification for memory port slices

Hans Baier · Aug 10, 2026, 11:55 PM UTC

65727d65d708

gen/fhdl: emit negative signed constants as $signed(N'h<pattern>)

Florent Kermarrec · Jul 24, 2026, 12:04 AM UTC

37b75bd468e2

doc: refresh unreleased ecosystem changelog

Florent Kermarrec · Jul 31, 2026, 7:12 AM UTC

3f01ef965837

Merge pull request #2541 from trabucayre/gowin_jtag

enjoy-digital · Jul 28, 2026, 8:05 AM UTC

97d81467881f

Merge pull request #2548 from trabucayre/rework_libxil

enjoy-digital · Jul 28, 2026, 7:26 AM UTC

11b3771467c2

Merge pull request #2547 from enjoy-digital/hyperram-l2-cache-integration

enjoy-digital · Jul 27, 2026, 5:10 PM UTC

67a912f121b4

soc: add optional L2 cache to HyperRAM integration

Florent Kermarrec · Jul 27, 2026, 4:51 PM UTC

6365b2f6ca2f

Merge pull request #2546 from enjoy-digital/efinix-trion-ddr-integration

enjoy-digital · Jul 27, 2026, 4:46 PM UTC

ec0692b3ded3

ram/efinix: add shared Trion DDR integration

Florent Kermarrec · Jul 27, 2026, 4:44 PM UTC

4ae619c0c7a8

Merge pull request #2545 from enjoy-digital/efinix-trion-v1-pll-feedback

enjoy-digital · Jul 27, 2026, 4:14 PM UTC

e2764b389903

build/efinix: omit feedback mode on Trion V1 PLLs

Florent Kermarrec · Jul 27, 2026, 3:34 PM UTC

5f1edbd9c926

Merge pull request #2544 from enjoy-digital/efinix-ddr-integration

enjoy-digital · Jul 27, 2026, 3:04 PM UTC

65c1e13006db

Merge pull request #2540 from FlyGoat/master

enjoy-digital · Jul 27, 2026, 2:58 PM UTC

10beb75ee18f

soc/cores/ram: add Efinix hard DDR integration

Florent Kermarrec · Jul 27, 2026, 2:18 PM UTC

3581e61d5f15

soc/cores/cpu/zynq7000,zynqmp/core.py: implements add_software_packages and prepare_software to handle libxil at this level

Gwenhael Goavec-Merou · Jul 27, 2026, 9:24 AM UTC

c6a5f6a6fe26

soc/cores/cpu/init.py,litex/soc/integration/builder.py: added generic methods (and call) to prepare custom specifics software package/code

Gwenhael Goavec-Merou · Jul 27, 2026, 9:23 AM UTC

e46bee08ed24

soc/software/libxil/init.py: added logic to clone/prepare the lib and fill headers

Gwenhael Goavec-Merou · Jul 27, 2026, 9:22 AM UTC

9980aee92d94

litex/build/gowin: integrates/enables JTAG support when Gowin toolchain is used

Gwenhael Goavec-Merou · Jul 25, 2026, 9:54 AM UTC

ef510fbd11fb

build/openocd.py: added ir code for USER1/USER2 on GW1N/GW2A

Gwenhael Goavec-Merou · Jul 25, 2026, 9:53 AM UTC

1635746a694f

soc/cores/jtag.py: added JTAG support for gowin GW1N and GW2A

Gwenhael Goavec-Merou · Jul 25, 2026, 9:52 AM UTC

7994470b7d2a

setup: support uv virtualenv installs

Jiaxun Yang · Jul 24, 2026, 11:35 AM UTC

8ac750af9db0

Merge pull request #2539 from rblilja/icestorm-missing-space

enjoy-digital · Jul 23, 2026, 6:52 AM UTC

93c8d230e2e7

Merge pull request #2537 from gatecat/nexusddrphy

enjoy-digital · Jul 22, 2026, 2:46 PM UTC

1f707879485c

build/lattice/icestorm: add trailing space to synth_opts to fix abc9/flow3

Robin · Jul 22, 2026, 2:42 PM UTC

11d783c0cd06

Merge pull request #2535 from hansfbaier/hierarchy-fix

enjoy-digital · Jul 22, 2026, 2:17 PM UTC

a2bb7bb34a9a

test/hdl: strengthen inline subtree regression.

Florent Kermarrec · Jul 22, 2026, 2:16 PM UTC

d60391cea375

Merge pull request #2534 from trabucayre/litex_setup_always_accept

enjoy-digital · Jul 22, 2026, 2:11 PM UTC

aa688fda73b9

setup: use standard --yes update confirmation.

Florent Kermarrec · Jul 22, 2026, 2:10 PM UTC

62c47eb1edfa

Merge pull request #2538 from enjoy-digital/openfpgaloader-device-selection

enjoy-digital · Jul 22, 2026, 2:06 PM UTC

701fbdc3ccb3

build/openfpgaloader: preserve constructor compatibility.

Florent Kermarrec · Jul 22, 2026, 2:03 PM UTC

5c42d5caf986

build: Add --device option to openFPGALoader

Bartosz M. Zabolotny · Jul 17, 2026, 2:14 PM UTC

04b37ddd1ad2

Merge pull request #2533 from OMouad/apicula-nextpnr-freq

enjoy-digital · Jul 22, 2026, 1:59 PM UTC

4e94910d8bab

build/gowin/apicula: account for generated system clock.

Florent Kermarrec · Jul 22, 2026, 1:55 PM UTC

bc731f0a449b

doc: update unreleased changelog

Florent Kermarrec · Jul 22, 2026, 1:35 PM UTC

e863401db997

liblitedram: Handle NEXUSDDRPHY defines

gatecat · Jul 21, 2026, 1:59 PM UTC

f0f4be1c2c98

test/hdl: regression test for inline-flag reset drop bug

Hans Baier · Jul 20, 2026, 9:33 PM UTC

f6627e1c22fb

fix hierarchical Verilog: don't reset inline flags during recursion

Hans Baier · Jul 20, 2026, 9:21 PM UTC

f6d21b29914f

litex_setup.py: added argument to bypass confirmation before updating when a repository is modified locally

Gwenhael Goavec-Merou · Jul 20, 2026, 2:48 PM UTC

8679dc4a60f0

build/gowin/apicula: pass design clock target to nextpnr via --freq.

Mouad Ouroui · Jul 19, 2026, 6:32 PM UTC

871d85007413

Merge pull request #2531 from enjoy-digital/video-framebuffer-integration-cleanup

enjoy-digital · Jul 16, 2026, 10:57 AM UTC

722f8ea29da0

test: exercise framebuffer DMA backends

Florent Kermarrec · Jul 16, 2026, 10:32 AM UTC

d368afb60e6b

video: generalize framebuffer memory integration

Florent Kermarrec · Jul 16, 2026, 10:32 AM UTC

57eb2dba32c4

Merge pull request #2527 from CauaBF1/feature/hyperram-framebuffer-support

enjoy-digital · Jul 16, 2026, 8:19 AM UTC

313593df406d

test: cover framebuffer DMA bus integration

Florent Kermarrec · Jul 16, 2026, 8:10 AM UTC

0fc5d3951664

soc: route framebuffer DMA through system bus

Florent Kermarrec · Jul 16, 2026, 8:09 AM UTC

e25bea69593a

Merge pull request #2519 from enjoy-digital/yosys-builtin-slang

enjoy-digital · Jul 16, 2026, 7:57 AM UTC

812665cf3521

Merge pull request #2530 from wcj007/fix-litedsp-branch-main

enjoy-digital · Jul 16, 2026, 4:26 AM UTC

c7a4b6512999

Set litedsp repo branch to main (default master branch no longer exists)

wcj007 · Jul 16, 2026, 12:46 AM UTC

d3f8bcf9c831

README: add LiteDSP to the ecosystem cores / CI status table

Florent Kermarrec · Jul 15, 2026, 5:38 PM UTC

6acf95906212

Merge pull request #2528 from enjoy-digital/litedsp_setup

enjoy-digital · Jul 15, 2026, 2:43 PM UTC

b6c608fa3343

Merge pull request #2526 from CauaBF1/feature/crg-clock-domain-names

enjoy-digital · Jul 15, 2026, 2:28 PM UTC

9aba7aebdccb

Merge pull request #2525 from CauaBF1/feature/test-periph-gen

enjoy-digital · Jul 15, 2026, 2:27 PM UTC

bd2a5199c5bd

Merge pull request #2524 from CauaBF1/feature/json2renode-tests

enjoy-digital · Jul 15, 2026, 2:27 PM UTC

163865ee4ccc

soc: remove unused AXI master helper

CauaBF1 · Jul 15, 2026, 2:15 PM UTC

8af19c9dde95

test: add LiteX JSON-to-Renode coverage

CauaBF1 · Jul 15, 2026, 1:19 PM UTC

3a52b37a88c0

soc: add HyperRAM and framebuffer tests

CauaBF1 · Jul 15, 2026, 1:18 PM UTC

f8f73efa892c

soc: add HyperRAM framebuffer support

CauaBF1 · Jul 15, 2026, 1:17 PM UTC

80dd37dc7a79

video: support Wishbone framebuffer DMA

CauaBF1 · Jul 15, 2026, 1:17 PM UTC

20c68a73ec56

build: explicitly name CRG clock domains

CauaBF1 · Jul 15, 2026, 1:16 PM UTC

77cd5bcbb32f

test: add LiteX peripheral generator coverage

CauaBF1 · Jul 15, 2026, 1:14 PM UTC

6ad764f4f112

litex_repos: add LiteDSP (portable RF/DSP building blocks, WIP)

Florent Kermarrec · Jul 15, 2026, 9:56 AM UTC

bda8a3268eb3

Commit history

wishbone/cache: share lane selection across read fast paths

wishbone/cache: optionally forward read-miss refill responses

wishbone/cache: add opt-in same-line read-burst fast path

bench: reject stale runs and fingerprint simulation builds

litex_sim: expose SDRAM L2 refill width for performance tuning

bench: measure CPU and memory cycles with LiteX Sim

Merge pull request #2565 from enjoy-digital/software-custom-sdram-init

software: allow custom SDRAM initialization

Merge pull request #2564 from trabucayre/zynq7000_ps7-mio_support

soc/cores/cpu/zynq7000/core.py: added MIO mode and pin configuration for add_can, add_uart, add_sdio, add_spi, add_i2c and add_ethernet

doc: update unreleased changelog

Merge pull request #2559 from rvodden/pr-setup-packaging

litex_setup: Install packaging>=24.2 alongside setuptools

Merge pull request #2561 from enjoy-digital/fix/axi-downconverter-narrow-serialization

soc/interconnect/axi: serialize narrow down-converter accesses

cpu/veer_eh1: align integration with LiteX conventions

Merge pull request #2556 from SilverLining-EDA/add-veer-eh1-cpu

cpu/vexiiriscv: implement flush_cpu_dcache() via Zicbom CBO sweep

litex_repos: point pythondata-cpu-veer_eh1 to litex-hub

Merge pull request #2554 from shenki/cva6-fixes

Merge pull request #2550 from hansfbaier/fix-hierarchical-memory-port-wire

Merge pull request #2553 from trabucayre/vhd2v_converter_fix_missing_params

Merge pull request #2552 from rvodden/pr-json2dts-i2c-buses

Merge pull request #2551 from blurbdust/stratixv-fixes

soc/software: wire up VeeR EH1 PIC interrupt init in isr.c

cpu/veer_eh1: add VeeR EH1 CPU core support

cpu/cva6: Export correct CLINT timebase

cpu/cva6: Export CPU_ISA, CPU_MMU and CLINT/PLIC regions for the DT

cpu/cva6: Mark the LiteX IO region (0x80000000+) non-idempotent

cpu/cva6: Move csr base to 0xf0000000 to avoid ethmac IO overlap

cpu/cva6: Cut AXI channels between atomics adapter and LiteX bus

cpu/cva6: Resolve AMOs/LR-SC in front of the LiteX bus

cpu/cva6: Map LiteX interrupt line to same numbered PLIC source

cpu/cva6: Fix PLIC NumSources mismatch

build/vhd2v_converter.py: when vhd files are not converted to verilog: keep p_xxx params in ip_params. Otherwise build may fails

build/vhd2v_converter.py: updates extract_prefixed_generics to pass target to extract_prefixed_generics (default value: GHDL)

build/converter_common.py: added target argument in extract_prefixed_generics to return a dict p_xxx: val when target is not GHDL

tools/json2dts: emit a node for every I2C bus, not just i2c0

build/openocd: add StratixV IR (0xe) to get_ir

litex/gen: fix hierarchical Verilog wire classification for memory port slices

gen/fhdl: emit negative signed constants as $signed(N'h<pattern>)

doc: refresh unreleased ecosystem changelog

Merge pull request #2541 from trabucayre/gowin_jtag

Merge pull request #2548 from trabucayre/rework_libxil

Merge pull request #2547 from enjoy-digital/hyperram-l2-cache-integration

soc: add optional L2 cache to HyperRAM integration

Merge pull request #2546 from enjoy-digital/efinix-trion-ddr-integration

ram/efinix: add shared Trion DDR integration

Merge pull request #2545 from enjoy-digital/efinix-trion-v1-pll-feedback

build/efinix: omit feedback mode on Trion V1 PLLs

Merge pull request #2544 from enjoy-digital/efinix-ddr-integration

Merge pull request #2540 from FlyGoat/master

soc/cores/ram: add Efinix hard DDR integration

soc/cores/cpu/zynq7000,zynqmp/core.py: implements add_software_packages and prepare_software to handle libxil at this level

soc/cores/cpu/__init__.py,litex/soc/integration/builder.py: added generic methods (and call) to prepare custom specifics software package/code

soc/software/libxil/__init__.py: added logic to clone/prepare the lib and fill headers

litex/build/gowin: integrates/enables JTAG support when Gowin toolchain is used

build/openocd.py: added ir code for USER1/USER2 on GW1N/GW2A

soc/cores/jtag.py: added JTAG support for gowin GW1N and GW2A

setup: support uv virtualenv installs

Merge pull request #2539 from rblilja/icestorm-missing-space

Merge pull request #2537 from gatecat/nexusddrphy

build/lattice/icestorm: add trailing space to synth_opts to fix abc9/flow3

Merge pull request #2535 from hansfbaier/hierarchy-fix

test/hdl: strengthen inline subtree regression.

Merge pull request #2534 from trabucayre/litex_setup_always_accept

setup: use standard --yes update confirmation.

Merge pull request #2538 from enjoy-digital/openfpgaloader-device-selection

build/openfpgaloader: preserve constructor compatibility.

build: Add --device option to openFPGALoader

Merge pull request #2533 from OMouad/apicula-nextpnr-freq

build/gowin/apicula: account for generated system clock.

doc: update unreleased changelog

liblitedram: Handle NEXUSDDRPHY defines

test/hdl: regression test for inline-flag reset drop bug

fix hierarchical Verilog: don't reset inline flags during recursion

litex_setup.py: added argument to bypass confirmation before updating when a repository is modified locally

build/gowin/apicula: pass design clock target to nextpnr via --freq.

Merge pull request #2531 from enjoy-digital/video-framebuffer-integration-cleanup

soc/cores/cpu/init.py,litex/soc/integration/builder.py: added generic methods (and call) to prepare custom specifics software package/code

soc/software/libxil/init.py: added logic to clone/prepare the lib and fill headers