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VexRiscv

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Commit history

Commits included in published releases. Unpublished intermediate commits are private. Showing matches from the latest 100 commits ending at this release.

Update .travis.yml

Dolu1990 · Feb 5, 2021, 1:51 PM UTC

7afe6cbef816

Update .travis.yml

Dolu1990 · Feb 5, 2021, 12:56 PM UTC

130733ab08b7

Update .travis.yml

Dolu1990 · Feb 5, 2021, 10:54 AM UTC

3dfbe0057e59

travis debug

Dolu1990 · Feb 3, 2021, 8:41 PM UTC

200faed1ae9c

SpinalHDL version++

Dolu1990 · Feb 1, 2021, 2:20 PM UTC

d92adfbad008

SpinalHDL version++

Dolu1990 · Feb 1, 2021, 11:28 AM UTC

6ee45a1014fb

fix regression.mk typo

Dolu1990 · Jan 30, 2021, 11:34 PM UTC

98eaeaabc894

Merge branch 'master' into dev

Dolu1990 · Jan 30, 2021, 7:30 PM UTC

6aa6191240ef

VexRiscvSmpLitex options refractoring

Dolu1990 · Jan 23, 2021, 7:16 PM UTC

d6e8a5ef2204

VexRiscvSmpLitex --in-order-decoder --wishbone-memory added

Dolu1990 · Jan 23, 2021, 4:48 PM UTC

ce143e06f236

Add vexRiscvConfig.withMmu option

Dolu1990 · Jan 21, 2021, 12:28 PM UTC

bcd140fc42cf

Merge pull request #163 from lindemer/pmp-warl

Dolu1990 · Jan 21, 2021, 9:50 AM UTC

50a69d8d4a19

Remove registers storing PMP region bounds

Samuel Lindemer · Jan 20, 2021, 1:16 PM UTC

6c13e6458f87

PMP registers are now WARL

Samuel Lindemer · Jan 20, 2021, 8:27 AM UTC

828ea9600670

Merge pull request #162 from lindemer/paging

Dolu1990 · Jan 18, 2021, 9:18 PM UTC

ed68c8cf0414

FPU sqrt functional

Dolu1990 · Jan 14, 2021, 5:33 PM UTC

04499c0b765d

fpu div functional, sqrt wip

Dolu1990 · Jan 14, 2021, 2:56 PM UTC

85dd5dbf8e32

Distinguish between page faults from MMU and access faults from PMP

Samuel Lindemer · Jan 14, 2021, 7:34 AM UTC

5e6c64546123

FpuCore can add/mul/fma/store/load

Dolu1990 · Jan 13, 2021, 5:28 PM UTC

8761d0d9eed9

Cfu add state index and cfu index

Dolu1990 · Jan 11, 2021, 12:43 PM UTC

6e0be6e18c97

DataCache increase syncPendingMax to 32 and use a sync queue instead of async one

Dolu1990 · Jan 1, 2021, 10:59 PM UTC

930bdf9ddab5

Add AES-instruction support

Dolu1990 · Dec 21, 2020, 10:50 AM UTC

780ad01ac092

Merge pull request #147 from lindemer/pmp

Dolu1990 · Dec 11, 2020, 2:22 PM UTC

d2855fcfca54

typo

Dolu1990 · Dec 11, 2020, 1:13 PM UTC

c59499ec0356

Add comments to the AesPlugin

Dolu1990 · Dec 11, 2020, 12:51 PM UTC

eaff52b26411

Add comments to the AesPlugin

Dolu1990 · Dec 11, 2020, 12:46 PM UTC

6da09967f8f7

Remove PMP from MachineOs test defaults

Samuel Lindemer · Dec 10, 2020, 8:39 AM UTC

7d699dcc1375

PMP plugin passes regression tests

Samuel Lindemer · Dec 7, 2020, 8:11 AM UTC

f2ce2eab002b

Add TOR support, tests pass on GenZephyr

Samuel Lindemer · Dec 4, 2020, 9:11 AM UTC

763eebeeba75

PMP passes test with GenZephyr, but pipeline flushes have been disabled

Samuel Lindemer · Dec 3, 2020, 4:29 PM UTC

5cb5061d9b4d

CfuPlugin improve writeback buffering

Dolu1990 · Dec 3, 2020, 3:21 PM UTC

9a6931a54cd7

Lock PMP address registers in golden model

Samuel Lindemer · Dec 2, 2020, 1:18 PM UTC

987de8fb6a28

Merge remote-tracking branch 'upstream/master' into pmp

Samuel Lindemer · Dec 2, 2020, 1:08 PM UTC

14c39a0070ca

Add PMP to golden model

Samuel Lindemer · Dec 2, 2020, 9:25 AM UTC

872aa19d8328

Add PMP test to regression suite

Samuel Lindemer · Dec 1, 2020, 5:35 PM UTC

d5b1a8f565c4

VexRiscvSmpClusterGen.dBusCmdMasterPipe option added

Dolu1990 · Dec 1, 2020, 12:51 PM UTC

45ff78d0685a

Add PMP regression test

Samuel Lindemer · Nov 26, 2020, 2:08 PM UTC

c5023ad973f4

remove libts-dev from readme

Dolu1990 · Nov 30, 2020, 3:11 PM UTC

1b65a9e52334

Flush pipeline after PMP CSR writes

Samuel Lindemer · Nov 25, 2020, 11:28 AM UTC

2d0ebf1ef55d

Fix Csr ReadWrite interration with DBusCachedPlugin execute halt

Dolu1990 · Nov 16, 2020, 11:37 AM UTC

e0ae46e79491

DBusCachedPlugin increase pendingMax to 64 to hide memory latency when saving a full context

Dolu1990 · Nov 16, 2020, 11:38 AM UTC

832218dbece7

Fix Csr ReadWrite interration with DBusCachedPlugin execute halt

Dolu1990 · Nov 16, 2020, 11:37 AM UTC

ba523c627a19

Merge pull request #150 from banahogg/patch-1

Dolu1990 · Nov 15, 2020, 10:25 AM UTC

dae633aa7d3e

Update GCC prebuild instructions for sifive.com reorg

banahogg · Nov 15, 2020, 1:31 AM UTC

d1691e947899

AesPlugin is now little endian

Dolu1990 · Nov 12, 2020, 2:07 PM UTC

c1b0869c211a

DBusCachedPlugin miss decoded aquire fix

Dolu1990 · Nov 12, 2020, 2:07 PM UTC

1b2a2ebaca8b

AesPlugin added, work with dropbear encryption, seem ok for decryption (barmetal)

Dolu1990 · Nov 2, 2020, 4:14 PM UTC

05e725174caa

RegFilePlugin.x0Init do less assumption on other plugin behaviour

Dolu1990 · Nov 2, 2020, 4:01 PM UTC

9abe19317def

Enable PMP register lock

Samuel Lindemer · Oct 28, 2020, 1:21 PM UTC

97fe279f7b0a

Do not allow jtag ebreak outside machine mode

Dolu1990 · Oct 28, 2020, 11:58 AM UTC

dc9246715de9

Fix CsrPlugin privilege crossing

Dolu1990 · Oct 28, 2020, 11:57 AM UTC

4209dc27929d

Do not allow jtag ebreak outside machine mode

Dolu1990 · Oct 28, 2020, 11:58 AM UTC

576e21d75d59

Fix CsrPlugin privilege crossing

Dolu1990 · Oct 28, 2020, 11:57 AM UTC

abebeaea1f46

Initial commit of PMP plugin

Samuel Lindemer · Oct 20, 2020, 9:45 AM UTC

fc2c8a7c371d

CfuBusParameter has now a few default values

Dolu1990 · Oct 23, 2020, 9:06 AM UTC

fe342c347c6e

Merge pull request #145 from zeldin/bigendian2

Dolu1990 · Oct 21, 2020, 10:56 AM UTC

d490f903ea08

Update big endian instruction encoding

Marcus Comstedt · Oct 20, 2020, 4:05 PM UTC

6c8e97f82584

DataCache split redo / refilling execute stage halt

Dolu1990 · Oct 19, 2020, 4:12 PM UTC

4ece59385d42

SpinalHDL++

Dolu1990 · Oct 16, 2020, 9:25 AM UTC

e58daee088b8

improve LightShifterPlugin arbitration halt timings

Dolu1990 · Oct 9, 2020, 9:37 AM UTC

ec55187033ea

Fix UserInterruptPlugin interrupt enable

Dolu1990 · Oct 9, 2020, 8:45 AM UTC

bbaa0520c061

Merge pull request #141 from betrusted-io/dev-asid

Dolu1990 · Oct 4, 2020, 1:20 PM UTC

8bd1785233df

Merge remote-tracking branch 'origin/dev' into dev-asid

bunnie · Oct 4, 2020, 11:53 AM UTC

72f85ef6c0b8

sbt update

Dolu1990 · Oct 4, 2020, 7:57 AM UTC

b7e7faebadb5

Add ASID field to SATP

bunnie · Oct 4, 2020, 7:34 AM UTC

65e6f6054bca

Merge pull request #135 from zeldin/bigendian

Dolu1990 · Oct 1, 2020, 2:43 PM UTC

98de02051e1a

Update README.md

Dolu1990 · Oct 1, 2020, 2:41 PM UTC

9d35e75fb597

dbus mmu access improvement

Dolu1990 · Sep 17, 2020, 8:06 PM UTC

3f5e771a5c27

add earlyBranch option to Smp config

Dolu1990 · Sep 13, 2020, 4:33 PM UTC

de820daf74dd

pipeline data cache unaligned access check

Dolu1990 · Sep 7, 2020, 10:01 AM UTC

49488d19afa5

Merge pull request #136 from zeldin/rv32e

Dolu1990 · Sep 6, 2020, 8:23 PM UTC

775b336ee01d

Add support for RV32E in RegFilePlugin

Marcus Comstedt · Sep 6, 2020, 3:05 PM UTC

8e466dd13c8a

fix CfuPlugin generation

Dolu1990 · Sep 4, 2020, 8:36 AM UTC

4c3cad97d3db

Add support for big endian byte ordering

Marcus Comstedt · Aug 30, 2020, 1:17 PM UTC

c489143442d9

VexRiscvSmpCluster now avoid useless decoder for plic/clint

Dolu1990 · Aug 13, 2020, 9:26 AM UTC

7dcaa0c390ee

Smp config now initialise regfile using logic

Dolu1990 · Jul 28, 2020, 2:15 PM UTC

69d5ba239a13

Litex cluster add DMA sel feature

Dolu1990 · Jul 21, 2020, 5:42 PM UTC

cc423cbe4956

Litex cluster can now set cache layout

Dolu1990 · Jul 21, 2020, 5:35 PM UTC

15bda15bc9f0

improve LitexCluster area for single core configuration

Dolu1990 · Jul 21, 2020, 1:45 PM UTC

9f62f375381b

Add VexRiscvLitexSmpClusterCmdGen

Dolu1990 · Jul 21, 2020, 1:07 PM UTC

da666ade4967

BmbGenerators refractoring (bus -> ctrl)

Dolu1990 · Jul 16, 2020, 11:04 AM UTC

fe5401f83510

Cleanup BmbGenerators

Dolu1990 · Jul 15, 2020, 6:51 PM UTC

da7331791256

BmbInterconnectGenerator refractoring

Dolu1990 · Jul 15, 2020, 3:03 PM UTC

5f0aec757051

Merge branch 'bmbRework' into dev

Dolu1990 · Jul 10, 2020, 11:06 AM UTC

4f5ba6b04480

Merge branch 'smp' into dev

Dolu1990 · Jul 10, 2020, 11:00 AM UTC

f6931784a5d3

Add openroad config

Dolu1990 · Jul 7, 2020, 11:37 PM UTC

d0a572de9885

DBusCachedPlugin now support asyncTagMemory

Dolu1990 · Jul 7, 2020, 11:36 PM UTC

32f778613fcb

Better VexRiscvSmpCluster config

Dolu1990 · Jul 7, 2020, 11:36 PM UTC

60ee7e2b4cfd

Fix MmuPlugin when used in multi stage config

Dolu1990 · Jul 5, 2020, 11:17 AM UTC

51070d0e69aa

Remove CsrPlugin redoInterface combinatorial depedency from execut_isStuck

Dolu1990 · Jul 5, 2020, 11:17 AM UTC

06584518da0c

Few fixes

Dolu1990 · Jul 5, 2020, 11:16 AM UTC

a404078117b6

Litex SoC add coherent DMA master

Dolu1990 · Jul 5, 2020, 11:15 AM UTC

c51e25f8c483

Got VexRiscvSmpLitexCluster refractoring to work

Dolu1990 · Jun 30, 2020, 8:29 PM UTC

32539dfe6de5

Bring back smp cluster parameters

Dolu1990 · Jun 29, 2020, 1:49 PM UTC

0da94ac66fd2

Update Bmb brides and comment out SmpCluster for now

Dolu1990 · Jun 29, 2020, 9:44 AM UTC

062509deee29

Fix inv regression

Dolu1990 · Jun 20, 2020, 11:18 AM UTC

c12f9a378d21

D$ inv/ack are now fragment, which ease serialisation of wider invalidations

Dolu1990 · Jun 19, 2020, 1:57 PM UTC

f0f2cf61daca

Fix DebugPlugin.fromBmb

Dolu1990 · Jun 19, 2020, 1:57 PM UTC

c18bc12cb20b

cleanup of old todo

Dolu1990 · Jun 19, 2020, 1:56 PM UTC

490c1f6b0276

SmpCluster now with proper jtag and plic

Dolu1990 · Jun 12, 2020, 2:18 PM UTC

b0cd88c4626b