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VexRiscv

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Commit history

Commits included in published releases. Unpublished intermediate commits are private. Showing matches from the latest 100 commits ending at this release.

#176 fix typo

Dolu1990 · Apr 22, 2021, 12:02 PM UTC

0a0998fcea10

update #176 when DebugPlugin ebreak are enabled it disable CsrPlugin ebreak. Also, DebugPlugin ebreak can be disabled via the debug bus.

Dolu1990 · Apr 22, 2021, 11:59 AM UTC

32e4ea406f52

implement #176 DebugPlugin.allowEBreak is now disabled until the debug bus is used.

Dolu1990 · Apr 20, 2021, 9:23 PM UTC

bfe65da1ebd8

remove eclipse plugin

Dolu1990 · Apr 12, 2021, 4:28 PM UTC

4e41654a84c1

CfuPlugin names fixes

Dolu1990 · Apr 2, 2021, 7:20 AM UTC

73893ce5d98d

IBusSimplePlugin ensure AHB persistance

Dolu1990 · Mar 31, 2021, 5:03 PM UTC

a42c0891196d

FpuCore improve FMA rounding

Dolu1990 · Mar 29, 2021, 2:31 PM UTC

9ac6625ef34d

Add AES/FPU doc

Dolu1990 · Mar 29, 2021, 12:55 PM UTC

a8721b02de82

Add rvc support and fix rvc with FPU

Dolu1990 · Mar 25, 2021, 1:14 PM UTC

9462496386b1

Fetcher.decompressor ensure that the decoded instruction do not mutate when the pipeline is stalled (fix FPU cmd fork for rvc without injector stage)

Dolu1990 · Mar 25, 2021, 1:13 PM UTC

6f481f51ef2b

fpu now lift wfi

Dolu1990 · Mar 24, 2021, 3:21 PM UTC

21c91c6b7086

RVC implement RVF RVD Rework RVC_GEN

Dolu1990 · Mar 24, 2021, 11:00 AM UTC

925edd160eda

Merge pull request #167 from rdolbeau/support_FDwC

Dolu1990 · Mar 24, 2021, 10:59 AM UTC

704423f27fe1

Attempt at supporting C (ompressed) and F/D (floating-point) together

Romain Dolbeau · Mar 24, 2021, 10:07 AM UTC

8495fe3dde0c

litex cluster add cpuPerFpu option

Dolu1990 · Mar 23, 2021, 7:00 PM UTC

da458dea7ee2

litex better pipelining for better fmax, create one FPU for each 4 cores

Dolu1990 · Mar 18, 2021, 10:10 AM UTC

80f64f0f9f0e

fpu add schedulerM2sPipe optino

Dolu1990 · Mar 18, 2021, 10:09 AM UTC

6956db2b21da

fpu cleanup

Dolu1990 · Mar 18, 2021, 9:54 AM UTC

099dea743b17

litex add fpu suport

Dolu1990 · Mar 17, 2021, 12:19 PM UTC

f6e620196de0

Merge branch 'fiber' into dev

Dolu1990 · Mar 17, 2021, 9:02 AM UTC

1a0aa37d6f43

fix fpu diagram

Dolu1990 · Mar 16, 2021, 1:52 PM UTC

530554d19ca2

Handle ClockDomain improvements

Dolu1990 · Mar 16, 2021, 1:46 PM UTC

e23687c45d28

fpu improve FMax and add asyncronus regfile support

Dolu1990 · Mar 16, 2021, 1:45 PM UTC

02c572b6f111

fpu add doc

Dolu1990 · Mar 16, 2021, 1:44 PM UTC

0d628b470658

fpu improve pipline cycles

Dolu1990 · Mar 15, 2021, 4:27 PM UTC

5aa1f2e9966e

data cache relax assert into error

Dolu1990 · Mar 15, 2021, 1:43 PM UTC

341c159d06e6

Merge branch 'dev' into fiber

Dolu1990 · Mar 15, 2021, 9:35 AM UTC

3a34b8dae20c

wipe generator

Charles Papon · Mar 11, 2021, 5:02 PM UTC

ff4e5e4666e7

FpuPlugin.pending is now 6 bits

Charles Papon · Mar 11, 2021, 12:06 PM UTC

adc37b269cc6

DebugPlugin.fromBscane2 added

Charles Papon · Mar 10, 2021, 7:35 PM UTC

845cfcb96618

fiber sync

Charles Papon · Mar 7, 2021, 7:43 PM UTC

67d2f72a4bd0

fiber update

Dolu1990 · Mar 5, 2021, 9:04 PM UTC

e384bfe1451a

fix cfu gen error

Dolu1990 · Mar 4, 2021, 7:29 PM UTC

fd234bbf9e38

CFU ensure that CFU_IN_FLIGHT do not produce false positive when the pipeline is stuck

Dolu1990 · Mar 4, 2021, 7:15 PM UTC

aee8841438d0

sync

Dolu1990 · Mar 4, 2021, 3:06 PM UTC

0530d22a1de1

Add MuraxAsicBlackBox example

Dolu1990 · Mar 4, 2021, 9:16 AM UTC

caf1bde49b64

fpu fix cmd / commit race condition

Dolu1990 · Mar 2, 2021, 6:39 PM UTC

4bdab667cccc

fpu now track commits using a counter per pipeline per port

Dolu1990 · Mar 2, 2021, 3:13 PM UTC

636d53cf639f

Improve subnormal/normal rounding

Dolu1990 · Feb 26, 2021, 3:32 PM UTC

81c193af1ff2

Fpu fix a few div special cases

Dolu1990 · Feb 25, 2021, 6:39 PM UTC

de81da36eb11

fpu added exact div/sqrt implementations using iterative approaches

Dolu1990 · Feb 25, 2021, 2:28 PM UTC

de09ed3fcb3d

CfuPlugin.response_ok removed

Dolu1990 · Feb 23, 2021, 11:23 AM UTC

be81cc1e0e18

fpu test cleaning

Dolu1990 · Feb 22, 2021, 6:27 PM UTC

47673863fb66

fpu fix arbitration/lock bugs add getVexRiscvRegressionArgs

Dolu1990 · Feb 22, 2021, 6:27 PM UTC

b1f4c06d4ec1

fpu vex regression goldenModel can now assert FPU interface

Dolu1990 · Feb 19, 2021, 4:55 PM UTC

a6e89fe05cf1

fpu fix exception flag handeling

Dolu1990 · Feb 19, 2021, 12:03 PM UTC

3f226b758c9a

fpu integration wip, got mandelbrot to work in linux with no inline (crash when inlined)

Dolu1990 · Feb 19, 2021, 10:26 AM UTC

e504afbf1897

fpu improve fmax

Dolu1990 · Feb 17, 2021, 3:35 PM UTC

8537d18b161c

fpu Fix VexRiscv integration and add software f64 tests (pass)

Dolu1990 · Feb 17, 2021, 11:33 AM UTC

1e647f799c87

MulPlugin fix buffer interraction with partial regfile bypass

Dolu1990 · Feb 17, 2021, 10:35 AM UTC

06b7a91de4b2

fpu double fixes DataCache now support wide load/store

Dolu1990 · Feb 16, 2021, 2:38 PM UTC

f180ba2fc96a

VexRIscvSmpCluster add options

Dolu1990 · Feb 16, 2021, 1:42 PM UTC

8b2a2afb6fbc

DataCache.toBmb with aggregation sync path pipelined

Dolu1990 · Feb 16, 2021, 1:17 PM UTC

1752b9e6d629

MulPlugin.outputBuffer feature added

Dolu1990 · Feb 16, 2021, 1:16 PM UTC

fe690528f7c3

VexRiscvConfig.get added

Dolu1990 · Feb 16, 2021, 1:15 PM UTC

3b99090879a0

fpu f64/f32 pass all tests

Dolu1990 · Feb 12, 2021, 1:48 PM UTC

7d3b35c32c64

fpu add FCVT_X_X

Dolu1990 · Feb 11, 2021, 4:40 PM UTC

9a25a1287971

fpu fix f32 tests for f64 fpu

Dolu1990 · Feb 11, 2021, 3:42 PM UTC

82dfd10dba4a

fpu f64 load/store/mv/mul seems ok

Dolu1990 · Feb 11, 2021, 3:07 PM UTC

b6eda1ad7a1e

fpu f64 wip

Dolu1990 · Feb 10, 2021, 6:27 PM UTC

e97c2de837b2

fpu f64 wip

Dolu1990 · Feb 10, 2021, 12:20 PM UTC

88dffc21f75f

fpu refractoring

Dolu1990 · Feb 10, 2021, 11:16 AM UTC

889cc5fde228

fpu fixed corner cases, FpuPlugin coupling, pass rv-test excepted div (accuracy), can run C sinf successfully

Dolu1990 · Feb 9, 2021, 5:35 PM UTC

1fe993ad10a1

fpu sgnj / fclass / fmv pass

Dolu1990 · Feb 8, 2021, 2:29 PM UTC

bf6a64b6b55c

fpu min max pass

Dolu1990 · Feb 6, 2021, 1:08 PM UTC

bf0829231dd5

fpu eq lt le pass testfloat

Dolu1990 · Feb 6, 2021, 12:20 PM UTC

008fadeaa926

fpu got exception flag right for add/sub/mul/i2f/f2i

Dolu1990 · Feb 5, 2021, 3:24 PM UTC

6170243283d7

VexRiscvSmpCluster can now set regfile read kind

Dolu1990 · Feb 5, 2021, 10:09 AM UTC

f278900cbe6a

fix synthesis bench

Dolu1990 · Feb 4, 2021, 11:41 AM UTC

0f1ca72171f0

fpu test wip

Dolu1990 · Feb 4, 2021, 11:41 AM UTC

936e5823dcdc

fix synthesis bench

Dolu1990 · Feb 4, 2021, 11:41 AM UTC

3710fd34928f

fpu load subnormal and i2f now use single cycle shifter

Dolu1990 · Feb 3, 2021, 3:48 PM UTC

02b5b9b05c94

Merge branch 'dev' into fpu

Dolu1990 · Feb 3, 2021, 3:06 PM UTC

8e7e736e3e6f

fpu wip

Dolu1990 · Jan 15, 2021, 1:03 PM UTC

8eb8356deafb

fpu f2i rounding ok and full shifter

Dolu1990 · Feb 3, 2021, 1:27 PM UTC

1d0eecdcb048

fpu moved 1 bit from round to mantissa

Dolu1990 · Feb 2, 2021, 10:29 AM UTC

ef011fa0d408

fpu i2f rounding ok

Dolu1990 · Feb 1, 2021, 3:12 PM UTC

a87cb202b1f4

SpinalHDL version++

Dolu1990 · Feb 1, 2021, 2:20 PM UTC

d92adfbad008

SpinalHDL version++

Dolu1990 · Feb 1, 2021, 11:28 AM UTC

6ee45a1014fb

fix regression.mk typo

Dolu1990 · Jan 30, 2021, 11:34 PM UTC

98eaeaabc894

Merge branch 'master' into dev

Dolu1990 · Jan 30, 2021, 7:30 PM UTC

6aa6191240ef

fpu mul now pass all roundings

Dolu1990 · Jan 29, 2021, 9:30 PM UTC

c51b0fcafe4e

fpu mul sems all good excepted subnormal rounding

Dolu1990 · Jan 29, 2021, 3:13 PM UTC

09975927686d

fpu moved overflow rounding to writeback

Dolu1990 · Jan 29, 2021, 1:37 PM UTC

3c4df1e963d1

fpu add rounding is ok excepted infinity result

Dolu1990 · Jan 28, 2021, 7:26 PM UTC

fc3e6a6d0a11

fpu added proper rounding for add (need to manage substraction)

Dolu1990 · Jan 27, 2021, 11:25 PM UTC

1ae84ea83b78

fpu now integrate f2i shifter withing the subnormal shifter

Dolu1990 · Jan 27, 2021, 11:11 AM UTC

195e4c422dc2

fpu merged i2f with load pipeline

Dolu1990 · Jan 26, 2021, 2:28 PM UTC

444bcdba0a04

fpu added more tests for min max sqrt div

Dolu1990 · Jan 26, 2021, 11:50 AM UTC

3334364f5f69

fpu got proper subnormal support, pass add/mul

Dolu1990 · Jan 26, 2021, 9:49 AM UTC

f818fb3ba43f

VexRiscvSmpLitex options refractoring

Dolu1990 · Jan 23, 2021, 7:16 PM UTC

d6e8a5ef2204

VexRiscvSmpLitex --in-order-decoder --wishbone-memory added

Dolu1990 · Jan 23, 2021, 4:48 PM UTC

ce143e06f236

fpu div implement some special values handeling

Dolu1990 · Jan 22, 2021, 7:47 PM UTC

bdb5bc118051

fpu mul now support special floats values and better rounding

Dolu1990 · Jan 22, 2021, 5:15 PM UTC

7d79685fe241

fpu add now support special floats values and better rounding

Dolu1990 · Jan 22, 2021, 1:55 PM UTC

4bd637cf8887

Add vexRiscvConfig.withMmu option

Dolu1990 · Jan 21, 2021, 12:28 PM UTC

bcd140fc42cf

fpu zero/nan wip

Dolu1990 · Jan 21, 2021, 11:13 AM UTC

ccd13b7e9ead

Merge pull request #163 from lindemer/pmp-warl

Dolu1990 · Jan 21, 2021, 9:50 AM UTC

50a69d8d4a19

Remove registers storing PMP region bounds

Samuel Lindemer · Jan 20, 2021, 1:16 PM UTC

6c13e6458f87

fpu add signed i2f/f2i

Dolu1990 · Jan 20, 2021, 12:15 PM UTC

ac5844f39305