Commits included in published releases. Unpublished intermediate commits are private. Showing matches from the latest 100 commits ending at this release.
#60 Added automated linux regression in travis Fix DBusCached plugin access sharing for the MMU deadlock when exception is in the decode stage Fix IBusSimplePlugin issues with used with non regular configs + MMU Bring back the LinuxGen config into a light one
Charles Papon · Apr 19, 2019, 3:35 PM UTC
e47b76fa6779
Fix emulator instruction emulation trap redirection to supervisor. Impact only AMO less configs
Charles Papon · Apr 19, 2019, 12:31 AM UTC
2810ff05b096
#60 Fix SFENCE_VMA deadlock
Charles Papon · Apr 18, 2019, 4:33 PM UTC
b79b02152b73
TestInduvidualFeatures now use the linux config + MMU
Charles Papon · Apr 14, 2019, 9:06 PM UTC
6f04c02cd25a
Fix non RVC fetcher exception PC capture
Charles Papon · Apr 14, 2019, 9:04 PM UTC
8c7407967eee
#60 Add sim error message on RVC instruction without RVC capabilities
Charles Papon · Apr 13, 2019, 8:44 AM UTC
61d25e931e45
Make regression sim great again
Charles Papon · Apr 13, 2019, 8:41 AM UTC
5d1ec604b252
riscv software model without RVC now trap on RVC instruction before pcWrite + 2
Charles Papon · Apr 13, 2019, 8:40 AM UTC
9ac1d3d59eec
README.md Update eclipse install
Charles Papon · Apr 12, 2019, 3:41 PM UTC
a12ca43284eb
Add CsrPlugin.userGen option which now remove privilegeReg when not set
Charles Papon · Apr 12, 2019, 2:37 PM UTC
3301a1b3640f
Merge remote-tracking branch 'origin/master' into linux
Charles Papon · Apr 12, 2019, 2:26 PM UTC
d5723968da7d
restore freertos tests
Charles Papon · Apr 12, 2019, 2:09 PM UTC
8421328ee127
#69 Relax address calculation of decode branch predictor by adding KEEP synthesis attribut
Charles Papon · Apr 12, 2019, 1:56 PM UTC
13b774b53562
Remove jalr from decode branch prediction missaligned inibition
Charles Papon · Apr 12, 2019, 1:27 PM UTC
41ff87f83b4d
Fix #69 discoverd fmax issue with decode stage branch predictions
Charles Papon · Apr 12, 2019, 1:24 PM UTC
63cd5f42aff0
Merge pull request #69 from tomverbeure/micro_warnings
Dolu1990 · Apr 12, 2019, 12:58 PM UTC
fdd2194c8fca
#60 Fix missing ecallGen flag
Charles Papon · Apr 11, 2019, 1:30 PM UTC
b329ee85ad03
Default linux config is now without RVC Remove all linux usless CSR from the config Remove verilator instruction fetch check
Charles Papon · Apr 10, 2019, 11:18 PM UTC
ece1e735475d
Reduce machine mode emulator CSR requirements and emulate more CSR (in the case they aren't supporter in hardware)
Charles Papon · Apr 10, 2019, 5:04 PM UTC
caa37a8028e2
Flush MMU line with exception on context switching instead than on cmd fire
Charles Papon · Apr 10, 2019, 1:42 PM UTC
6b2259496144
shorter coremark
Charles Papon · Apr 10, 2019, 1:41 PM UTC
926b74a203ba
Add coremark
Charles Papon · Apr 10, 2019, 1:41 PM UTC
189cadfbb33b
Fix DebugPlugin -> force machine mode, force uncached memory load
Charles Papon · Apr 9, 2019, 10:35 PM UTC
d7f6c18c0ab5
Fix icache test when dynamic target branch prediction is enabled
Charles Papon · Apr 9, 2019, 5:37 PM UTC
9b6b65b8b41c
Added lrsc/amo tests
Charles Papon · Apr 9, 2019, 5:27 PM UTC
a6dc53044140
Add hardware AMO, require AMO=yes in sim and withAmo=true in linux.scala
Charles Papon · Apr 8, 2019, 11:22 PM UTC
fd42e7701e12
Clean and fix things to get all the non-linux configs and machine only configs working
Charles Papon · Apr 8, 2019, 2:06 PM UTC
21cb8615fdbc
#60 Fix instruction cache refill
Charles Papon · Apr 8, 2019, 12:24 PM UTC
32921491b81e
#60 Fix machine mode emulator atomic emulation. Do not write regfile if the page was set as read only.
Charles Papon · Apr 8, 2019, 11:20 AM UTC
fd15a938c5a3
Add a busy flag from MMU ports iBus/dBus now halt on MMU busy, which avoid looping forever on page fault
Charles Papon · Apr 8, 2019, 9:38 AM UTC
c2595273ec4c
#60 Fix MMU holding invalid tlb, while linux is assuming it isn't doing so.
Charles Papon · Apr 7, 2019, 1:44 PM UTC
f89ee0d422a3
Complain about wrong earlyBranch settings.
Tom Verbeure · Apr 6, 2019, 7:58 PM UTC
4fd36454d7cc
GenMicroNoCsr: no memory stage, no write-back stage
Tom Verbeure · Apr 6, 2019, 7:38 PM UTC
39a4aa5e2627
Merge branch 'linuxDev' into linux
Charles Papon · Apr 6, 2019, 12:01 AM UTC
ffafc27104d4
workaround Verilator comparaison linting
Charles Papon · Apr 6, 2019, 12:00 AM UTC
6df3e578431e
update todo, nothing todo ? everything done ?
Charles Papon · Apr 5, 2019, 11:42 PM UTC
21b4ae8f2ff6
Rework CsrPlugin exception delegation
Charles Papon · Apr 5, 2019, 9:40 PM UTC
e7f3dd55537a
Add more delegation tests Reduce dcache test duration
Charles Papon · Apr 5, 2019, 8:56 PM UTC
ddf0f0683424
Rework CsrPlugin interrupt delegation
Charles Papon · Apr 5, 2019, 8:55 PM UTC
acaa931e1179
Move user mode page fault checkes from iBus/dBus plugin into the MmuPlugin SUM was in fact already supported
Charles Papon · Apr 5, 2019, 7:34 PM UTC
9e72971ff0df
update todolist
Charles Papon · Apr 5, 2019, 6:04 PM UTC
82c894932a57
Add dcache tests
Charles Papon · Apr 5, 2019, 6:03 PM UTC
aeb418a99e74
Fix DataCache flush on the last line
Charles Papon · Apr 5, 2019, 6:02 PM UTC
5a6665e57f8b
add icache flush test
Charles Papon · Apr 5, 2019, 4:11 PM UTC
8459d423b823
rework i$ flush
Charles Papon · Apr 5, 2019, 4:11 PM UTC
60a41bfc75a3
Look like precise fence.i isn't required in practice
Charles Papon · Apr 5, 2019, 4:08 PM UTC
f5d4e745c70d
Centralised all todo in linux.scala Sorted out fence fence.i instruction in iBus/dBus plugins. Fixed MMU permitions while in used mode and bypassing the MMU
Charles Papon · Apr 5, 2019, 10:17 AM UTC
446e9625af01
Fix RVC instruction cache xtval allignement
Charles Papon · Apr 4, 2019, 11:08 PM UTC
888e1c0b8a3a
Got the debug plugin working with the linux config (had to disable CSR ebreak)
Charles Papon · Apr 4, 2019, 10:25 PM UTC
8e6010fd712b
Change LR/SC to reserve the whole memory Fix MPP access from other plugins Got all the common configuration to compile and pass regression excepted the debugger one First synthesis results
Charles Papon · Apr 4, 2019, 6:34 PM UTC
4f0a02594cc4
cleaning
Charles Papon · Apr 4, 2019, 10:59 AM UTC
f8b438d9dce1
Removing D$ reports
Charles Papon · Apr 3, 2019, 12:47 PM UTC
de1c9c6fea04
Got multiway I$ D$ running linux fine.
Charles Papon · Apr 3, 2019, 12:33 PM UTC
3f7a859e07dd
Add data cache flush feature
Charles Papon · Apr 3, 2019, 1:56 PM UTC
922c18ee495a
Got the MMU refilling itself with datacache cached memory access instead of io accesses
Charles Papon · Apr 3, 2019, 12:32 PM UTC
066f562c5efb
#60 Got the new data cache design passing all tests and running linux
Charles Papon · Apr 2, 2019, 9:44 PM UTC
8be40e637b60
#60 Got the new instruction cache design passing the standard regressions
Charles Papon · Apr 1, 2019, 10:26 PM UTC
fd4da7708424
#60 Got instruction cache running linux :D
Charles Papon · Apr 1, 2019, 9:59 AM UTC
bc0af02c9742
#60 Fix interrupt causing fetch privilege issues
Charles Papon · Apr 1, 2019, 8:47 AM UTC
1dff9aff8a31
Better simulation console integration
Charles Papon · Apr 1, 2019, 8:31 AM UTC
e74a5a71eb76
#60 Sync everything, added much comment on the top of Linux.scala to help reproduce
Charles Papon · Mar 31, 2019, 9:43 PM UTC
369a3d0f5f81
Got buildroot login, userspace, commands working Moved location of DTB, initrd. Will move again Added getChar SBI in emulator Added an QEMU mode in the emulator config.h, work with qemu riscv32 virt
Charles Papon · Mar 31, 2019, 1:17 PM UTC
c7314cc6060d
Add qemu command
Dolu1990 · Mar 30, 2019, 5:29 PM UTC
de500ad8f92e
Add a qemu option (wip)
Dolu1990 · Mar 30, 2019, 5:26 PM UTC
9383445e0b96
#60 Fix software model. Forgot physical address for on RVC instruction
Charles Papon · Mar 30, 2019, 10:24 AM UTC
1a36f2689df5
#60 Fix instruction fetch exception PC by forcing LSB to be zero
Charles Papon · Mar 30, 2019, 9:10 AM UTC
29980016f382
Better fix
Dolu1990 · Mar 29, 2019, 8:18 AM UTC
9fff41934676
#60 should fix the first instruction fetch privilege after interrupt
Dolu1990 · Mar 29, 2019, 8:02 AM UTC
391cff69d33d
Sync impact less changes (asfar i know)
Dolu1990 · Mar 29, 2019, 7:43 AM UTC
0c4872961166
Merge branch 'master' of https://github.com/SpinalHDL/VexRiscv
Fix cacheless LR/SC xtval, did some SRC/ADD_SUB/ALU redesign
Dolu1990 · Mar 27, 2019, 5:58 PM UTC
0bed511a6c22
Add prerequired stuff
Dolu1990 · Mar 27, 2019, 9:55 AM UTC
43c3922a3d9e
Added a neutral LINUX_SOC for sim purposes
Dolu1990 · Mar 27, 2019, 9:53 AM UTC
f113946e6675
#60 user space reached /sbin/init: error while loading shared libraries: libm.so.6: cannot stat shared object: Error 38
Dolu1990 · Mar 26, 2019, 11:26 PM UTC
b69c474fa266
Fix some models missmatch Add more SBI Add hardware LR/SC support in dbus cacheless
Dolu1990 · Mar 26, 2019, 12:25 AM UTC
94fc2c3ecf51
Fix mprv and add it into the softare model
Dolu1990 · Mar 25, 2019, 11:03 AM UTC
1c3fd5c38bc0
Fix mprv
Dolu1990 · Mar 25, 2019, 10:47 AM UTC
1ec11dc03df9
Add MMU MPRIV for easier machinemode emulation #60
Dolu1990 · Mar 25, 2019, 9:30 AM UTC
c34f5413a3ea
Merge pull request #67 from tomverbeure/manual
Dolu1990 · Mar 25, 2019, 1:07 AM UTC
d63c6818df8c
Machine mode emulator
Dolu1990 · Mar 25, 2019, 1:00 AM UTC
9d55283b3ba2
Merge branch 'master' of https://github.com/SpinalHDL/VexRiscv
Tom Verbeure · Mar 24, 2019, 11:56 PM UTC
3d5e941aefbe
Add PlicCost test
Dolu1990 · Mar 24, 2019, 11:17 AM UTC
e28702eb4055
#60 Add LitexSoC workspace / linux loading. Need to emulate peripherals and adapte the kernel now. Probably also need some machine mode emulation Software time !
Dolu1990 · Mar 24, 2019, 9:52 AM UTC
6c0608f0dd69
Merge pull request #66 from tomverbeure/IBusSimple_to_PipelinedMemoryBus
Dolu1990 · Mar 24, 2019, 7:05 AM UTC
d70f970b15fa
Same thing for DBusSimpleBus.
Tom Verbeure · Mar 23, 2019, 11:36 PM UTC
ea62fd0e1676
Ignore vim backup files.
Tom Verbeure · Mar 23, 2019, 10:34 PM UTC
1afad4f240fb
Make toPipelinedMemoryBus() just like the other busses
Tom Verbeure · Mar 23, 2019, 10:32 PM UTC
95c3e436dcee
Make xtval more compliant
Dolu1990 · Mar 23, 2019, 7:12 PM UTC
0656a49332f8
Fix csrrs/csrrc for xip registers
Dolu1990 · Mar 23, 2019, 5:11 PM UTC
7159237104ed
CSR Plugin now implement interruptions as specified in the spec