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VexRiscv

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Commit history

Commits included in published releases. Unpublished intermediate commits are private. Showing matches from the latest 100 commits ending at this release.

Fix VexRiscvSmpClusterGen without linux debug minimal features

Dolu1990 · Feb 8, 2023, 10:28 AM UTC

692f604dd5ee

Add EmbeddedRiscvJtag.debugCd

Dolu1990 · Nov 28, 2022, 10:04 AM UTC

eafeb5fe493e

comment debug code

Dolu1990 · Nov 21, 2022, 1:02 PM UTC

a25ae96d33a4

Privileged debug fake maskmax to 31

Dolu1990 · Nov 21, 2022, 1:01 PM UTC

572ca3fcfa10

Fix CsrPlugin dcsr.stepie

Dolu1990 · Nov 21, 2022, 10:55 AM UTC

5a8cdee884a9

Merge pull request #276 from LYWalker/master

Dolu1990 · Nov 18, 2022, 4:38 PM UTC

4ae738690442

Clear mprv on xretAwayFromMachine

Dolu1990 · Nov 17, 2022, 2:03 PM UTC

e19e59b55ce8

Privileged debug now implement stoptime stopcount

Dolu1990 · Nov 17, 2022, 12:58 PM UTC

663174bc7319

ensure rvc 0 is detected as a illegal instruction

Dolu1990 · Nov 17, 2022, 10:03 AM UTC

36c3346e51a6

Fix RISC-V debug hardware breakpoints

Dolu1990 · Nov 14, 2022, 1:45 PM UTC

5e17ab62d699

Fix a few RISC-V official debug support : - Disable interrupts in debug mode - Ensure traps do not change CSR in debug mode - step will also consider trapEvent

Dolu1990 · Nov 11, 2022, 1:05 PM UTC

fe68b8494e10

RISC-V debug havereset implemented

Dolu1990 · Nov 10, 2022, 2:49 PM UTC

2504f9b9b971

main.cpp add VEXRISCV_JTAG=yes

Dolu1990 · Nov 10, 2022, 12:43 PM UTC

0bfaf06a4ace

Remove rv64 opcode (shift and lwu) Thanks Milan

Dolu1990 · Oct 27, 2022, 1:44 PM UTC

f71234786ff1

fix regression

Dolu1990 · Oct 27, 2022, 1:38 PM UTC

d70794f25206

Fix regression compilation

Dolu1990 · Oct 27, 2022, 1:20 PM UTC

5d0deb20b354

Add GenFullWithRiscvPrivilegedDebugJtag demo

Dolu1990 · Oct 27, 2022, 12:55 PM UTC

9f6186cd9a62

Merge branch 'riscv-debug' into dev

Dolu1990 · Oct 27, 2022, 12:46 PM UTC

6289ebcbe498

CsrPlugin now force privilegeGen when withPrivilegedDebug is enabled

Dolu1990 · Oct 26, 2022, 1:48 PM UTC

a6c29766da07

fix diagram name

Dolu1990 · Oct 26, 2022, 8:48 AM UTC

ab7b2cff3b99

Add VexRiscvAxi4LinuxPlicClint diagram drawio

Dolu1990 · Oct 26, 2022, 8:47 AM UTC

7fd55c78514e

cleaning

Dolu1990 · Oct 26, 2022, 8:25 AM UTC

0e531515ac6e

VexRiscvAxi4Linux now integrate Plic and Clint

Dolu1990 · Oct 26, 2022, 8:15 AM UTC

63dd787bcebb

Add VexRiscvAxi4Linux (untested, but generate a netlist)

Dolu1990 · Oct 24, 2022, 8:35 AM UTC

220af95043c3

Add whitebox example

Dolu1990 · Oct 24, 2022, 8:24 AM UTC

0979f8ba805d

privileged debug now access data cache with caching enable

Dolu1990 · Oct 21, 2022, 4:58 PM UTC

17d52ce58f65

CsrOpensbi now add rvc to misa

Dolu1990 · Oct 21, 2022, 4:58 PM UTC

486d17d24559

Fix privileged debug trigger decode break logic

Dolu1990 · Oct 21, 2022, 3:21 PM UTC

662943522fc1

riscv debug multiple harts

Dolu1990 · Oct 21, 2022, 10:28 AM UTC

95c656ceef2f

Fix RISCV debug step

Dolu1990 · Oct 20, 2022, 8:36 AM UTC

0313f84419ab

Add official RISC-V debug support (WIP, but can already load / step / run code via openocd telnet)

Dolu1990 · Oct 19, 2022, 10:36 AM UTC

4cd3f6529672

Fpu now set csr status fs on FPU csr write

Dolu1990 · Oct 6, 2022, 9:13 AM UTC

959e48a353b6

add litex --wishbone-force-32b

Dolu1990 · Sep 6, 2022, 9:18 AM UTC

fda7da00c21f

use SpinalHDL "dev"

Dolu1990 · Jul 22, 2022, 7:33 AM UTC

e3e21994b429

getDrivingReg() update

Dolu1990 · Jul 21, 2022, 7:10 AM UTC

54412bde30af

SpinalHDL 1.7.2

Dolu1990 · Jul 11, 2022, 10:02 AM UTC

a650000f0b20

csr opensbi now enable ebreak

Dolu1990 · Jun 13, 2022, 2:34 PM UTC

b1252f47de08

CfuPlugin.withEnable added

Dolu1990 · Jun 9, 2022, 3:57 PM UTC

1303c0ca7c42

fix VexRiscvRegressionData url

Dolu1990 · Jun 1, 2022, 7:53 AM UTC

1ce4c6e4932a

VexRiscvBmbGenerator now also report bytesPerLine

Dolu1990 · May 24, 2022, 10:37 AM UTC

0f6d0f022c6b

Better cache invalidation doc

Dolu1990 · May 24, 2022, 10:15 AM UTC

771eaf431e75

Add D$ single line flush support

Dolu1990 · May 24, 2022, 10:13 AM UTC

e6dfcac0be3c

Fix MPP to only retain legal values

Dolu1990 · May 24, 2022, 9:14 AM UTC

4c4913c70383

VexRiscvBmbGenerator export more info

Dolu1990 · May 24, 2022, 8:19 AM UTC

209fc719e8a0

Add VexRiscvSmpCluster forceMisa/forceMscratch

Dolu1990 · May 23, 2022, 1:49 PM UTC

48cf4120f2e5

Fix DYNAMIC_TARGET / debug plugin interation corrupting the recoded next pc durring step by step #254

Dolu1990 · May 17, 2022, 6:44 PM UTC

087285238784

Fix DYNAMIC_TARGET from triggering fetch missprediction while in debug mode #254

Dolu1990 · May 17, 2022, 1:27 PM UTC

a553d3b4767a

Fix CfuPlugin/VfuPlugin fork duplication https://github.com/google/CFU-Playground/issues/582

Dolu1990 · May 16, 2022, 8:36 AM UTC

78f0a7f13e05

Fix RVC step by step triggering next instruction branch predictor

Dolu1990 · May 11, 2022, 12:10 PM UTC

8df2dcbd4088

Update build.sbt

Dolu1990 · May 3, 2022, 10:03 PM UTC

6326736401c2

SpinalHDL 1.7.1

Dolu1990 · Apr 29, 2022, 1:22 PM UTC

27772a65dd5f

SpianlHDL 1.7.0

Dolu1990 · Apr 29, 2022, 12:16 PM UTC

9506b0b8f196

Merge pull request #248 from dnltz/WIP/dnltz/fix-reg

Dolu1990 · Apr 22, 2022, 9:12 AM UTC

8a8e9764939b

plugin: caches: Fix "Can't resolve the literal value of"

Daniel Schultz · Apr 20, 2022, 9:16 AM UTC

ea7a18c7f401

#241 Fix Murax/Briey TB timeouts

Dolu1990 · Apr 11, 2022, 9:59 AM UTC

3b8270b82bfb

#240 Code generation now warn against cpu generation without illegal instruction catch and ebreak being disabled, as it may make crash some software, ex : rust

Dolu1990 · Apr 8, 2022, 9:09 AM UTC

db3403359372

Merge pull request #243 from andreasWallner/fix_gen_simd_add_resetvector

Dolu1990 · Apr 4, 2022, 8:16 AM UTC

e6c21996a467

Fix reset vector of GenCustomSimdAdd

Andreas Wallner · Apr 2, 2022, 4:22 PM UTC

2d2017465e49

deprecated Data.keep

Dolu1990 · Mar 30, 2022, 2:17 PM UTC

ccff48f872a7

Update CFU example

Dolu1990 · Mar 23, 2022, 5:58 PM UTC

4bddb091aef6

Add MuraxCfu

Dolu1990 · Mar 23, 2022, 5:54 PM UTC

5dc91a8be484

CfuPlugin now implement upstream spec

Dolu1990 · Mar 23, 2022, 5:54 PM UTC

b2e61caf9e62

DecoderPlugin now implement forceIllegal API

Dolu1990 · Mar 23, 2022, 5:53 PM UTC

9149c420657c

Fix VexRiscvSmpClusterGen linux less mhartid

Dolu1990 · Mar 18, 2022, 11:36 AM UTC

51b8865b6661

Fix Briey simulation floating rxd blocking the uart #238

Dolu1990 · Feb 22, 2022, 3:15 PM UTC

e558b7958216

Merge branch 'master' into dev

Dolu1990 · Feb 17, 2022, 3:27 PM UTC

9d3b83366c1a

Merge pull request #236 from dnltz/WIP/dnltz/remove-assert

Dolu1990 · Feb 17, 2022, 3:25 PM UTC

36f57d5eb717

SpinalHDL 1.6.4

Dolu1990 · Feb 16, 2022, 1:26 PM UTC

5b45ddab1b20

SpinalHDL 1.6.5

Dolu1990 · Feb 16, 2022, 1:12 PM UTC

e4fde184d906

plugin: DBusSimplePlugin: Remove assert

Daniel Schultz · Feb 10, 2022, 6:55 PM UTC

807aa98d37f3

Merge branch 'dev'

Dolu1990 · Feb 5, 2022, 11:08 AM UTC

77e361e91e93

Merge branch 'master' into dev

Dolu1990 · Feb 5, 2022, 10:32 AM UTC

57146802789a

version++

Dolu1990 · Feb 5, 2022, 10:31 AM UTC

62c07670af07

verilator++

Dolu1990 · Feb 4, 2022, 3:36 PM UTC

4dd650736f4e

verilator++

Dolu1990 · Feb 4, 2022, 3:20 PM UTC

378c0f87233c

verilator++

Dolu1990 · Feb 4, 2022, 2:10 PM UTC

8b2f107d4620

Merge pull request #233 from dnltz/WIP/dnltz/csr-registers

Dolu1990 · Jan 27, 2022, 11:05 AM UTC

7d9a50357ffb

plugin: CsrPlugin: Init cycle and instret registers

Daniel Schultz · Jan 26, 2022, 7:59 AM UTC

57dd80a5667a

updated related to JtagInstructionWrapper.ignoreWidth

Dolu1990 · Jan 14, 2022, 8:59 AM UTC

9c34a1fd2e2b

syncronize golden model with dut for lrsc reservation

Dolu1990 · Jan 10, 2022, 6:55 PM UTC

b8e904e43f82

sim golden model lrsc reservation sync

Dolu1990 · Jan 10, 2022, 3:08 PM UTC

6e77f320871e

Fix lrsc from last commit

Dolu1990 · Jan 10, 2022, 1:21 PM UTC

da53de360f2e

DataCache.withInternalLrSc reserved clearing fix

Dolu1990 · Jan 10, 2022, 12:39 PM UTC

f46ad43f393c

Merge pull request #230 from OscarShiang/typo

Dolu1990 · Jan 4, 2022, 10:02 AM UTC

349993b23578

Fix typo in Linux.scala

Oscar Shiang · Jan 4, 2022, 8:31 AM UTC

fe6c391fe434

Enable scala 2.13 compatibility

Dolu1990 · Dec 20, 2021, 8:38 AM UTC

34e5cafb7514

Enable scala 2.13 compatibility

Dolu1990 · Dec 20, 2021, 8:38 AM UTC

4824827b7ed6

Update build.properties

Dolu1990 · Dec 18, 2021, 8:11 AM UTC

a34079884093

Update build.properties

Dolu1990 · Dec 18, 2021, 8:10 AM UTC

53a333034092

Merge branch dev (SpinalHDL 1.6.1)

Dolu1990 · Dec 15, 2021, 8:22 AM UTC

dd12047aa7e4

SpinalHDL 1.6.2

Dolu1990 · Dec 8, 2021, 10:45 PM UTC

0539dd7110ed

Merge pull request #220 from BLangOS/patch-1

Dolu1990 · Nov 15, 2021, 8:25 AM UTC

6c5908f7a35c

Update DebugPlugin.scala

B.Lang · Nov 11, 2021, 11:12 AM UTC

411d946a58fd

#213 disable pmp test with region overlapping

Dolu1990 · Oct 22, 2021, 3:24 PM UTC

acf14385d803

Merge pull request #213 from occheung/pmp-fix

Dolu1990 · Oct 21, 2021, 8:13 AM UTC

9df704cad942

pmp perm: revert to mux for priority

occheung · Oct 19, 2021, 3:40 AM UTC

a3807660e370

pmp_setter: fix mask generation

occheung · Oct 19, 2021, 3:39 AM UTC

df03c99ab2a8

IBusSimplePlugin can now use a Vec based buffer

Dolu1990 · Oct 13, 2021, 2:26 PM UTC

c3c3a94c5db5

VexRiscvSmpCluster add d$ i$ less arg

Dolu1990 · Oct 8, 2021, 11:19 AM UTC

97a3c1955b05

Fix BrieySim (SpinalSim)

Dolu1990 · Sep 25, 2021, 11:28 AM UTC

35754a070963