Commits included in published releases. Unpublished intermediate commits are private. Showing matches from the latest 100 commits ending at this release.
#60 Added automated linux regression in travis Fix DBusCached plugin access sharing for the MMU deadlock when exception is in the decode stage Fix IBusSimplePlugin issues with used with non regular configs + MMU Bring back the LinuxGen config into a light one
Charles Papon · Apr 19, 2019, 3:35 PM UTC
e47b76fa6779
#60 Add sim error message on RVC instruction without RVC capabilities
Charles Papon · Apr 13, 2019, 8:44 AM UTC
61d25e931e45
riscv software model without RVC now trap on RVC instruction before pcWrite + 2
Charles Papon · Apr 13, 2019, 8:40 AM UTC
9ac1d3d59eec
Merge remote-tracking branch 'origin/master' into linux
Charles Papon · Apr 12, 2019, 2:26 PM UTC
d5723968da7d
restore freertos tests
Charles Papon · Apr 12, 2019, 2:09 PM UTC
8421328ee127
Default linux config is now without RVC Remove all linux usless CSR from the config Remove verilator instruction fetch check
Charles Papon · Apr 10, 2019, 11:18 PM UTC
ece1e735475d
Add coremark
Charles Papon · Apr 10, 2019, 1:41 PM UTC
189cadfbb33b
Fix DebugPlugin -> force machine mode, force uncached memory load
Charles Papon · Apr 9, 2019, 10:35 PM UTC
d7f6c18c0ab5
Added lrsc/amo tests
Charles Papon · Apr 9, 2019, 5:27 PM UTC
a6dc53044140
Add hardware AMO, require AMO=yes in sim and withAmo=true in linux.scala
Charles Papon · Apr 8, 2019, 11:22 PM UTC
fd42e7701e12
Merge branch 'linuxDev' into linux
Charles Papon · Apr 6, 2019, 12:01 AM UTC
ffafc27104d4
Add dcache tests
Charles Papon · Apr 5, 2019, 6:03 PM UTC
aeb418a99e74
add icache flush test
Charles Papon · Apr 5, 2019, 4:11 PM UTC
8459d423b823
Got the debug plugin working with the linux config (had to disable CSR ebreak)
Charles Papon · Apr 4, 2019, 10:25 PM UTC
8e6010fd712b
Change LR/SC to reserve the whole memory Fix MPP access from other plugins Got all the common configuration to compile and pass regression excepted the debugger one First synthesis results
Charles Papon · Apr 4, 2019, 6:34 PM UTC
4f0a02594cc4
#60 Got the new data cache design passing all tests and running linux
Charles Papon · Apr 2, 2019, 9:44 PM UTC
8be40e637b60
#60 Got the new instruction cache design passing the standard regressions
Charles Papon · Apr 1, 2019, 10:26 PM UTC
fd4da7708424
#60 Got instruction cache running linux :D
Charles Papon · Apr 1, 2019, 9:59 AM UTC
bc0af02c9742
Better simulation console integration
Charles Papon · Apr 1, 2019, 8:31 AM UTC
e74a5a71eb76
#60 Sync everything, added much comment on the top of Linux.scala to help reproduce
Charles Papon · Mar 31, 2019, 9:43 PM UTC
369a3d0f5f81
Got buildroot login, userspace, commands working Moved location of DTB, initrd. Will move again Added getChar SBI in emulator Added an QEMU mode in the emulator config.h, work with qemu riscv32 virt
Charles Papon · Mar 31, 2019, 1:17 PM UTC
c7314cc6060d
#60 Fix software model. Forgot physical address for on RVC instruction
#60 user space reached /sbin/init: error while loading shared libraries: libm.so.6: cannot stat shared object: Error 38
Dolu1990 · Mar 26, 2019, 11:26 PM UTC
b69c474fa266
Fix some models missmatch Add more SBI Add hardware LR/SC support in dbus cacheless
Dolu1990 · Mar 26, 2019, 12:25 AM UTC
94fc2c3ecf51
Fix mprv and add it into the softare model
Dolu1990 · Mar 25, 2019, 11:03 AM UTC
1c3fd5c38bc0
Machine mode emulator
Dolu1990 · Mar 25, 2019, 1:00 AM UTC
9d55283b3ba2
#60 Add LitexSoC workspace / linux loading. Need to emulate peripherals and adapte the kernel now. Probably also need some machine mode emulation Software time !
Dolu1990 · Mar 24, 2019, 9:52 AM UTC
6c0608f0dd69
Make xtval more compliant
Dolu1990 · Mar 23, 2019, 7:12 PM UTC
0656a49332f8
Fix csrrs/csrrc for xip registers
Dolu1990 · Mar 23, 2019, 5:11 PM UTC
7159237104ed
CSR Plugin now implement interruptions as specified in the spec