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VexRiscv

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Update readme with the new ICache implementation

Dolu1990 · Feb 18, 2018, 10:48 PM UTC

d0e963559af8

Add jump priority managment in PcPlugins

Dolu1990 · Feb 16, 2018, 1:27 PM UTC

93110d3b953d

New faster/smaller/multi way instruction cache design. Single or dual stage

Dolu1990 · Feb 16, 2018, 1:21 AM UTC

506e0e3f60cc

Remap Briey/Murax onChipRam to 0x80000000 to avoid having memory at the null pointer location Commit missing file Update dhrystone hex to use GP. 1.44 DMIPS/Mhz

Dolu1990 · Feb 5, 2018, 3:16 PM UTC

d4b05ea3655b

Add CsrInterface to allow custom CSR addition Add CustomCsrDemoPlugin as a show case

Dolu1990 · Jan 31, 2018, 5:13 PM UTC

30b05eaf969d

Add DYNAMIC_TARGET branch prediction (1.41 DMIPS/Mhz) Add longer timeouts in the regressions tests

Dolu1990 · Jan 29, 2018, 12:17 PM UTC

0d318ab6b9fa

CsrPlugin : Now wait that the whole pipeline (including writeback) is empty before executing interruptions. This make the separation between context switching clear and avoid on atomic instructions failure

Dolu1990 · Jan 4, 2018, 4:37 PM UTC

43d3ffd6855c

Fix DecodingSimplePlugin model building when reinvocation is done one a preexisting opcode. add Atomic test flow

Dolu1990 · Jan 4, 2018, 1:43 PM UTC

4637e6cb4801

Merge pull request #6 from plex1/master

Dolu1990 · Oct 17, 2017, 10:17 PM UTC

9d75349d7a1c

updated main.cpp added missing using namespace std

Ubuntu · Oct 17, 2017, 10:09 PM UTC

008a5b730959