Commits included in published releases. Unpublished intermediate commits are private. Showing matches from the latest 100 commits ending at this release.
Merge remote-tracking branch 'origin/rework_jump_flush' into dev
Charles Papon · Jun 15, 2019, 4:09 PM UTC
60c9c094a763
Cleaning and remove BlockQ regression
Charles Papon · Jun 11, 2019, 10:00 PM UTC
c8ab99cd0bce
Add regression concurrent os executions flag to avoid running debug plugin tests
Merge remote-tracking branch 'origin/master' into dev
Charles Papon · Apr 29, 2019, 2:56 PM UTC
02db756b2104
Merge branch 'linux'
Dolu1990 · Apr 25, 2019, 9:20 PM UTC
6fc5406901fc
Add configs without memory/writeback stages in regressions Add rfReadInExecute configs in regressions Fix ShiftPluginLight and DBusSimplePlugin for configs with rfReadInExecute stage configs
Charles Papon · Apr 25, 2019, 3:36 PM UTC
d64589cc48a7
update Riscv software model lrsc implementation
Charles Papon · Apr 23, 2019, 7:55 PM UTC
266bdccc2e50
Longer linux regression timeout for very slow configs
Charles Papon · Apr 21, 2019, 8:16 PM UTC
c6dbaa52f68e
Riscv software model now implement interrupt priority accordingly to https://github.com/riscv/riscv-isa-sim/commit/496c59d064961bb81e63e2bba1bdadd4abf05a52#diff-a38d447c5232bd448697af4c6c8adb1a changes
Charles Papon · Apr 21, 2019, 6:01 PM UTC
14efe6ffda78
remove interrupt assertion
Charles Papon · Apr 21, 2019, 5:45 PM UTC
d7ca153c8b3e
Update Zephyr tests, the mem_pool_threadsafe one was bugy by the past, and now it is just too long
Charles Papon · Apr 21, 2019, 3:58 PM UTC
0e10c460c301
Look like zephyr mem_pool_threadsafe is a broken test
Charles Papon · Apr 21, 2019, 3:48 PM UTC
4cbb93cfc80b
Increase liveness trigger to allow large instruction cache flush
Dolu1990 · Apr 21, 2019, 1:25 PM UTC
1c86bf751423
Bring freertos back in tests Better travis test range
Charles Papon · Apr 21, 2019, 10:50 AM UTC
963805ad4868
Add zephyr tests
Charles Papon · Apr 21, 2019, 12:56 AM UTC
edde3e3011e4
Merge remote-tracking branch 'origin/linuxDev' into linux
#60 Added automated linux regression in travis Fix DBusCached plugin access sharing for the MMU deadlock when exception is in the decode stage Fix IBusSimplePlugin issues with used with non regular configs + MMU Bring back the LinuxGen config into a light one
Charles Papon · Apr 19, 2019, 3:35 PM UTC
e47b76fa6779
#60 Add sim error message on RVC instruction without RVC capabilities
Charles Papon · Apr 13, 2019, 8:44 AM UTC
61d25e931e45
riscv software model without RVC now trap on RVC instruction before pcWrite + 2