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dvb_fpga

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Commit history

Commits included in published releases. Unpublished intermediate commits are private. Showing matches from the latest 100 commits ending at this release.

Fix frame sequence issue when consuming data too slowly

suoto · Apr 25, 2022, 10:49 PM UTC

180e52ab0806

Added extra debug registers

suoto · Apr 25, 2022, 5:42 PM UTC

14a5cbdbc36e

Bit interleaver relies on addr wrap around, depth must be a power of 2

suoto · Apr 24, 2022, 4:15 PM UTC

c352cc09f8ee

Added monitoring output of bit interleaver

suoto · Apr 24, 2022, 3:28 PM UTC

a7bdc11a0dd3

Fixed constellation mapper and other misc changes

suoto · Apr 24, 2022, 3:23 PM UTC

32a78872d186

Renamed 'not_set' enum name to 'unknown'

suoto · Apr 21, 2022, 6:54 PM UTC

98f2b8968d32

Need to use a single BB frame otherwise other tests fail

suoto · Apr 17, 2022, 5:56 PM UTC

728a0169e4be

Removed unnecessary axi debug instance

suoto · Apr 16, 2022, 7:53 PM UTC

330b7813191d

Fixed GHDL sim getting stuck

suoto · Apr 16, 2022, 7:52 PM UTC

ba8ae39ad8ff

Using correct tlast to determine the first word received

suoto · Apr 15, 2022, 7:52 PM UTC

161ede114160

Merge remote-tracking branch 'origin/master' into pluto_sdr_trial

suoto · Apr 11, 2022, 11:18 AM UTC

5809b6932b10

Frame config is now embedded in the input data stream

suoto · Apr 10, 2022, 8:26 PM UTC

ae397ce7f3e7

Removed ployphase filter coefficients from register map

suoto · Apr 6, 2022, 6:23 PM UTC

2beda5070d84

WIP - removing polyphase filter from the encoder

suoto · Apr 2, 2022, 8:03 PM UTC

a0f89acb9361

Fixed input data filename in the dvbs2_encoder_tb

suoto · Mar 31, 2022, 5:29 PM UTC

da845c4a5cd5

Simplified/fixed CI scripts

suoto · Mar 31, 2022, 5:28 PM UTC

1187ed32f71f

Fixed 32APSK constellation scaling

suoto · Mar 31, 2022, 4:24 PM UTC

79c85595b6b5

Fixing CI run script

suoto · Mar 31, 2022, 3:43 PM UTC

342e6a6a73e7

Updating github CI hook

suoto · Mar 31, 2022, 3:30 PM UTC

a45433d64544

Updating run_tests.sh to use ghdl/vunit:llvm docker image

suoto · Mar 29, 2022, 8:43 PM UTC

6710a148881f

Updating FPGA cores repo

suoto · Mar 29, 2022, 8:39 PM UTC

dcab9de290f3

Python style fixes

suoto · Mar 29, 2022, 8:38 PM UTC

af50ae09581b

Updating flow diagram to GNU Radio 3.8+

suoto · Mar 29, 2022, 8:28 PM UTC

f1568b3b6fd1

Scaling modulator output/constellation mapper table

suoto · Mar 29, 2022, 8:23 PM UTC

980e76488eec

Moving custom docker image to Alpine Linux

suoto · Mar 29, 2022, 8:20 PM UTC

20db58aff772

Updating file names in the BB scrambler TB

suoto · Mar 27, 2022, 12:00 PM UTC

a1ecd5336c5b

Updating GR Python script to use 3.8+

suoto · Mar 27, 2022, 11:59 AM UTC

1f38e3dc5727

Improved error info on failed calls to GNU Radio script

Andre Souto · Mar 24, 2022, 12:49 PM UTC

025bbaeac4ca

Fixing yosys/ghdl issues

suoto · Mar 18, 2022, 10:37 AM UTC

9a07bd67c794

Merge branch 'master' into pluto_sdr_trial

suoto · Mar 18, 2022, 10:18 AM UTC

8e8812fb44d9

Adding bbframe length enforcer to handle more generic input streams

suoto · Mar 18, 2022, 10:15 AM UTC

87c4ef05caca

Hard wiring metadata to normal, QPSK, 2/3

suoto · Mar 3, 2022, 9:40 PM UTC

6086756d3a1c

Bypassing polyphase filter

suoto · Mar 3, 2022, 9:37 PM UTC

06cbc7cdd91c

Using ROM for constellation mapping

suoto · Mar 3, 2022, 9:10 PM UTC

0c625c3c3f28

Making metadata internal

suoto · Mar 3, 2022, 9:10 PM UTC

68f91e4af161

Link to zc706 block design was wrong

suoto · Jan 28, 2022, 10:25 AM UTC

0b482498f3ee

Working around GHDL issue (cannot handle IIR_KIND_INDEXED_NAME)

suoto · Jan 25, 2022, 12:21 AM UTC

e9efbf98a091

Script was incorrectly affecting all files in the project

suoto · Jan 18, 2022, 10:59 PM UTC

05f28550b878

LDPC encoder didn't handle slow input data properly

suoto · Oct 30, 2021, 1:42 PM UTC

438211ccde6a

Switching internals from big to little endianness

suoto · Oct 30, 2021, 1:41 PM UTC

ff32f66a56c6

Fixes to LiteFury board

suoto · Oct 30, 2021, 1:38 PM UTC

6a55201516a2

Data width and IQ width now both have generics

suoto · Oct 4, 2021, 8:51 PM UTC

d1a1cd73240f

Adding Vivado log/journal files to .gitignore

suoto · Oct 3, 2021, 12:22 PM UTC

a12b4252488a

Added LiteFury board; moved board build scripts to board/

suoto · Oct 3, 2021, 12:21 PM UTC

66ff9ba8ef6f

Minor code style changes

suoto · Sep 27, 2021, 8:06 PM UTC

ab116a061f25

AXI file compare complex now supports dumping multiple frames

suoto · Sep 27, 2021, 8:06 PM UTC

de61c7779b32

Removed code commited by mistake

suoto · Sep 27, 2021, 7:21 PM UTC

2118fd226377

Updating components status

suoto · Sep 27, 2021, 12:11 PM UTC

736a8bc70a62

Minor style fixes

suoto · Sep 26, 2021, 6:35 PM UTC

d249b466e62e

Using a separate FIFO for configuration

suoto · Sep 18, 2021, 2:23 PM UTC

940fa64dfdef

Adding readme for the ZC706 design

suoto · Aug 18, 2021, 7:02 PM UTC

d7b33e78d09a

Adding build scripts for ZC706 dev board

suoto · Aug 18, 2021, 6:22 PM UTC

924ad27c60c7

Updating fpga_cores

suoto · Jun 29, 2021, 8:57 PM UTC

c3fe650c5923

Fixed a combinatorial loop issue

suoto · Jun 29, 2021, 4:41 PM UTC

daeaa16228b6

Adapting to changes to fpga_cores

suoto · Jun 28, 2021, 11:52 AM UTC

d0c86387fa92

Path to constraints was not absoulte

suoto · Jun 28, 2021, 11:22 AM UTC

f9c46cade271

Changed license to CERN-OWH-W; renamed dvbs2_tx to dvbs2_encoder

suoto · Jun 19, 2021, 10:08 PM UTC

dc8a4cc17a2e

Added resource usage breakdown to README and minor tidy ups

suoto · Apr 4, 2021, 1:54 PM UTC

0cd693666699

Updating to fpga_cores/master

suoto · Mar 28, 2021, 12:41 AM UTC

c3e573d01efb

s_tdata with undefined was mistakenly passing

suoto · Mar 25, 2021, 3:37 PM UTC

12381026e13d

Polyphase coefficients are now generated alongside other sim files

suoto · Mar 25, 2021, 3:35 PM UTC

8aa961f1e39b

Changed polyphase filter number of taps to 33 (down from 101)

suoto · Mar 25, 2021, 2:27 PM UTC

e280668d71fb

Changing dvbs2_tx_tb output tolerance to 64 (from 1200)

suoto · Mar 25, 2021, 1:02 PM UTC

69c336a9726a

Renamed axi_file_compare_tolerance to axi_file_compare_complex

suoto · Mar 25, 2021, 12:55 PM UTC

3d7d51000484

Improved/fixed mapping RAM update handling

suoto · Mar 25, 2021, 12:51 PM UTC

ed0504c9e641

Generating bit mapper values based on the correct GNU Radio version

suoto · Mar 25, 2021, 12:50 PM UTC

870d12c7168f

Updated constellation mapper TB to use axi_file_compare_tolerance

suoto · Mar 25, 2021, 12:50 PM UTC

2108c310c826

Preferring enumerated types in the interfaces

suoto · Mar 25, 2021, 12:47 PM UTC

10e6682c7c08

Avoiding deadlock between s_constellation (input) and s_tready (output)

suoto · Mar 25, 2021, 12:46 PM UTC

b686a69b9c7c

Removed delay between plframe and polyphase filter

suoto · Mar 24, 2021, 2:54 PM UTC

df66e0212e81

Fixing file references in Yosys and Vivado build scripts

suoto · Mar 24, 2021, 2:16 PM UTC

aa150ecf798b

Updating fpga_cores

suoto · Mar 22, 2021, 5:58 PM UTC

d7244c1bc563

Removing dvbs2_tx_tb from GHDL runs as it now needs Verilog code

suoto · Mar 22, 2021, 5:44 PM UTC

f42218360a2f

Updating mapping RAM only if needed

suoto · Mar 22, 2021, 5:35 PM UTC

a342898cb9ce

Adjusting PL frame and output error tolerance

suoto · Mar 22, 2021, 5:34 PM UTC

594d204a5c30

Limiting check to GNU Radio's file length

suoto · Mar 22, 2021, 5:33 PM UTC

39da734c18a3

Added optional file dump to axi_file_compare_tolerance

suoto · Mar 22, 2021, 3:17 PM UTC

1967222cb8bf

Fixed data with for some AXI debug

suoto · Mar 22, 2021, 2:29 PM UTC

5e4a4f4f3076

Adding plframe and polyphase filter out debug

suoto · Mar 22, 2021, 1:50 AM UTC

fe5f88cbdcac

Fixed error % calculation inside axi file compare tolerance

suoto · Mar 21, 2021, 3:23 PM UTC

72ef5f2bc2a8

Adding AXI stream debug instances

suoto · Mar 21, 2021, 3:22 PM UTC

4b3c59c484c5

Renamed config inputs, added PL scrambler SR init to reg map

suoto · Mar 20, 2021, 10:55 PM UTC

47dd79c8e1e3

Removing old unused code

suoto · Mar 20, 2021, 5:00 PM UTC

ac4fb5a1d967

Changed taps to 101 for debugging tlast issue; cleaning up

suoto · Mar 20, 2021, 4:54 PM UTC

cc746da01fc1

Updating reg map to support 512 bytes space for polyphase coefficients

suoto · Mar 17, 2021, 9:55 PM UTC

921f066fbfab

Fixing DVB S2 TX testbench (WIP)

suoto · Mar 17, 2021, 9:55 PM UTC

3707e2d27846

Moving airhdl files to third_party/airhdl

suoto · Mar 16, 2021, 6:14 PM UTC

402d91471910

Fixed bit mapper RAM and FIR filter addressing

suoto · Mar 9, 2021, 1:08 AM UTC

d46034a32fc0

Adding AXI delay to break tvalid/tready deadlock

suoto · Mar 8, 2021, 10:00 PM UTC

8fe56db94519

(WIP) Moving AXI register map to dvbs2_tx

suoto · Mar 7, 2021, 5:07 PM UTC

a2a9679cb008

Corrected incorrect port widths

yrrapt · Mar 6, 2021, 10:43 AM UTC

7b1693d3718d

Merge pull request #10 from yrrapt/development

Thomas Parry · Mar 1, 2021, 9:22 PM UTC

4afb062d260d

Added coefficient clock and reset which are needed if AXI lite and stream are on differnt clock domains

yrrapt · Mar 1, 2021, 9:19 PM UTC

efbe71dcb7eb

Updated polyphase filter

yrrapt · Feb 27, 2021, 2:57 PM UTC

5ab7ba3f6044

wip - debugging polyphase filter

suoto · Feb 25, 2021, 10:25 AM UTC

19166b0758bb

added polyphase filter update procedure to the top level TB

suoto · Feb 22, 2021, 5:36 PM UTC

4907c3ba5109

Fixed tb compilation

suoto · Feb 22, 2021, 10:54 AM UTC

886dafe9fb0d

Promoted config and status stuff to ports for now

suoto · Feb 21, 2021, 2:58 PM UTC

043634070771

Preliminary work on adding polyphase filter

suoto · Feb 20, 2021, 9:24 PM UTC

91a32299608f

LDPC FIFO was set way too big by mistake

suoto · Feb 17, 2021, 2:22 AM UTC

a02d9bbd26ff