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dvb_fpga

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Commit history

Commits included in published releases. Unpublished intermediate commits are private. Showing matches from the latest 100 commits ending at this release.

Replacing polyphase filter verilog files with VHD

suoto · Jun 25, 2021, 3:12 PM UTC

cd79fdeb8465

Cleaning up

suoto · Jun 25, 2021, 3:05 PM UTC

52e3762bfd67

Replacing axi_stream_duplicate with axi_stream_replicate

suoto · Jun 25, 2021, 3:03 PM UTC

df4d4b2a2c82

Minor style changes in run.py

suoto · Jun 24, 2021, 11:18 AM UTC

b5320f7b067f

WIP - polyphase filter rework, first frame went through

suoto · Jun 24, 2021, 11:15 AM UTC

8c2e66d3134e

Switching license to CERN-OHL-W

suoto · Jun 19, 2021, 4:03 PM UTC

45ccf525fa53

Changing default data width to 8

suoto · Apr 17, 2021, 8:42 AM UTC

d8826c1d55c2

Replacing dvbs2_tx with dvbs2_encoder

suoto · Apr 9, 2021, 8:16 AM UTC

5a2253052a69

Added resource usage breakdown to README and minor tidy ups

suoto · Apr 4, 2021, 1:54 PM UTC

0cd693666699

Updating to fpga_cores/master

suoto · Mar 28, 2021, 12:41 AM UTC

c3e573d01efb

s_tdata with undefined was mistakenly passing

suoto · Mar 25, 2021, 3:37 PM UTC

12381026e13d

Polyphase coefficients are now generated alongside other sim files

suoto · Mar 25, 2021, 3:35 PM UTC

8aa961f1e39b

Changed polyphase filter number of taps to 33 (down from 101)

suoto · Mar 25, 2021, 2:27 PM UTC

e280668d71fb

Changing dvbs2_tx_tb output tolerance to 64 (from 1200)

suoto · Mar 25, 2021, 1:02 PM UTC

69c336a9726a

Renamed axi_file_compare_tolerance to axi_file_compare_complex

suoto · Mar 25, 2021, 12:55 PM UTC

3d7d51000484

Improved/fixed mapping RAM update handling

suoto · Mar 25, 2021, 12:51 PM UTC

ed0504c9e641

Generating bit mapper values based on the correct GNU Radio version

suoto · Mar 25, 2021, 12:50 PM UTC

870d12c7168f

Updated constellation mapper TB to use axi_file_compare_tolerance

suoto · Mar 25, 2021, 12:50 PM UTC

2108c310c826

Preferring enumerated types in the interfaces

suoto · Mar 25, 2021, 12:47 PM UTC

10e6682c7c08

Avoiding deadlock between s_constellation (input) and s_tready (output)

suoto · Mar 25, 2021, 12:46 PM UTC

b686a69b9c7c

Removed delay between plframe and polyphase filter

suoto · Mar 24, 2021, 2:54 PM UTC

df66e0212e81

Fixing file references in Yosys and Vivado build scripts

suoto · Mar 24, 2021, 2:16 PM UTC

aa150ecf798b

Updating fpga_cores

suoto · Mar 22, 2021, 5:58 PM UTC

d7244c1bc563

Removing dvbs2_tx_tb from GHDL runs as it now needs Verilog code

suoto · Mar 22, 2021, 5:44 PM UTC

f42218360a2f

Updating mapping RAM only if needed

suoto · Mar 22, 2021, 5:35 PM UTC

a342898cb9ce

Adjusting PL frame and output error tolerance

suoto · Mar 22, 2021, 5:34 PM UTC

594d204a5c30

Limiting check to GNU Radio's file length

suoto · Mar 22, 2021, 5:33 PM UTC

39da734c18a3

Added optional file dump to axi_file_compare_tolerance

suoto · Mar 22, 2021, 3:17 PM UTC

1967222cb8bf

Fixed data with for some AXI debug

suoto · Mar 22, 2021, 2:29 PM UTC

5e4a4f4f3076

Adding plframe and polyphase filter out debug

suoto · Mar 22, 2021, 1:50 AM UTC

fe5f88cbdcac

Fixed error % calculation inside axi file compare tolerance

suoto · Mar 21, 2021, 3:23 PM UTC

72ef5f2bc2a8

Adding AXI stream debug instances

suoto · Mar 21, 2021, 3:22 PM UTC

4b3c59c484c5

Renamed config inputs, added PL scrambler SR init to reg map

suoto · Mar 20, 2021, 10:55 PM UTC

47dd79c8e1e3

Removing old unused code

suoto · Mar 20, 2021, 5:00 PM UTC

ac4fb5a1d967

Changed taps to 101 for debugging tlast issue; cleaning up

suoto · Mar 20, 2021, 4:54 PM UTC

cc746da01fc1

Updating reg map to support 512 bytes space for polyphase coefficients

suoto · Mar 17, 2021, 9:55 PM UTC

921f066fbfab

Fixing DVB S2 TX testbench (WIP)

suoto · Mar 17, 2021, 9:55 PM UTC

3707e2d27846

Moving airhdl files to third_party/airhdl

suoto · Mar 16, 2021, 6:14 PM UTC

402d91471910

Fixed bit mapper RAM and FIR filter addressing

suoto · Mar 9, 2021, 1:08 AM UTC

d46034a32fc0

Adding AXI delay to break tvalid/tready deadlock

suoto · Mar 8, 2021, 10:00 PM UTC

8fe56db94519

(WIP) Moving AXI register map to dvbs2_tx

suoto · Mar 7, 2021, 5:07 PM UTC

a2a9679cb008

Corrected incorrect port widths

yrrapt · Mar 6, 2021, 10:43 AM UTC

7b1693d3718d

Merge pull request #10 from yrrapt/development

Thomas Parry · Mar 1, 2021, 9:22 PM UTC

4afb062d260d

Added coefficient clock and reset which are needed if AXI lite and stream are on differnt clock domains

yrrapt · Mar 1, 2021, 9:19 PM UTC

efbe71dcb7eb

Updated polyphase filter

yrrapt · Feb 27, 2021, 2:57 PM UTC

5ab7ba3f6044

wip - debugging polyphase filter

suoto · Feb 25, 2021, 10:25 AM UTC

19166b0758bb

added polyphase filter update procedure to the top level TB

suoto · Feb 22, 2021, 5:36 PM UTC

4907c3ba5109

Fixed tb compilation

suoto · Feb 22, 2021, 10:54 AM UTC

886dafe9fb0d

Promoted config and status stuff to ports for now

suoto · Feb 21, 2021, 2:58 PM UTC

043634070771

Preliminary work on adding polyphase filter

suoto · Feb 20, 2021, 9:24 PM UTC

91a32299608f

LDPC FIFO was set way too big by mistake

suoto · Feb 17, 2021, 2:22 AM UTC

a02d9bbd26ff

Fixed LDPC core testbench

suoto · Feb 17, 2021, 1:53 AM UTC

0357908ad060

Added axi_stream_frame_fifo to Yosys build file

suoto · Feb 16, 2021, 1:34 PM UTC

2edd6ef1bff4

Fixed LDPC table test

suoto · Feb 16, 2021, 1:27 PM UTC

6981ffd97a5a

misc fixes; added frames in flight counter

suoto · Feb 16, 2021, 1:06 AM UTC

337e4d274c7a

Updating fpga_cores

suoto · Feb 16, 2021, 12:03 AM UTC

362a2c33def3

Physical layer framer was not getting config properly

suoto · Feb 15, 2021, 11:58 PM UTC

b46e8deedca8

Added support for TID

suoto · Feb 15, 2021, 11:43 PM UTC

ec42a0d86436

Physical layer framer complete. Adding support for arbitrary input data widths

suoto · Feb 14, 2021, 11:32 PM UTC

6d4964adad4d

Tweaks to work around GHDL synth issues

suoto · Feb 14, 2021, 3:47 PM UTC

4c2d137abc61

Adding missing files to Yosys build file

suoto · Feb 14, 2021, 3:46 PM UTC

14a23536ed60

Mapped dummy frame ctrl to transmitter top level

suoto · Feb 14, 2021, 3:27 PM UTC

b1508d9f3b63

Tidying up

suoto · Feb 14, 2021, 2:27 PM UTC

a7281b4e0549

Updating README with status and usage numbers

suoto · Feb 14, 2021, 2:24 PM UTC

1a4dd9cb8d58

Frame FIFO for the complete PLFRAME is a bad idea

suoto · Feb 14, 2021, 2:19 PM UTC

bf2fae916157

Waiving Vivado's null vectors critical warning to warning

suoto · Feb 14, 2021, 2:18 PM UTC

c589c85ca213

Serializing header locally instead of via width converter

suoto · Feb 14, 2021, 2:11 PM UTC

00bf1f5657b1

Explicitly disabling width converter tkeep processing

suoto · Feb 14, 2021, 2:02 PM UTC

d7f1ea797182

Config is passed via TID now, no need for config_fifo

suoto · Feb 14, 2021, 1:05 PM UTC

3ed48beb0e09

Added physical layer framer to the transmitter top level

suoto · Feb 13, 2021, 6:45 PM UTC

76fc33ad2f8f

Adding dummy frame generator; cleaning up unused code/constants/generics

suoto · Feb 13, 2021, 6:32 PM UTC

27fe8763447f

Adding physical layer scrambler and framer

suoto · Feb 9, 2021, 11:15 PM UTC

ae3bc1282e14

Adding constellation mapper and fixes to dvbs2_tx

suoto · Feb 7, 2021, 1:37 AM UTC

357e28cc7a8a

Moved sin/cos functions to dvb_utils_pkg; removed unused includes

suoto · Feb 1, 2021, 10:32 PM UTC

acc5f8b192ee

Adding QPSK to the constellation types tested

suoto · Jan 31, 2021, 10:00 PM UTC

0c533671c351

Adding axi_plframe_header module

suoto · Jan 31, 2021, 12:25 PM UTC

fe6ff0edbe17

Updated to fpga_cores latest

suoto · Jan 2, 2021, 12:48 PM UTC

1b79ef0644b9

Working around a GHDL issue that was causing Yosys to fail

suoto · Nov 15, 2020, 8:28 PM UTC

3bfc18a07704

Reworked github actions files

suoto · Nov 15, 2020, 8:09 PM UTC

303a4298a344

Merge pull request #8 from phase4ground/plinsert

Andre Souto · Oct 27, 2020, 11:31 AM UTC

8a0f085a10c5

dvb_fpga: black formatting.

Anshul Makkar · Sep 21, 2020, 11:00 AM UTC

a962810a37bc

dvb_fpga: resolve formatting bug.

Anshul Makkar · Sep 21, 2020, 10:59 AM UTC

4cda7a7f99c8

Update README.md

anshul makkar · Sep 21, 2020, 10:54 AM UTC

45e0587d081d

Update run.py

anshul makkar · Sep 21, 2020, 10:53 AM UTC

dae02914504d

Dumping fixed point modulator's output

suoto · Sep 20, 2020, 1:34 PM UTC

095a4274e96d

Also dumping of physical layer framer w pilots off

suoto · Sep 19, 2020, 4:39 PM UTC

8ead86281e6d

Dumping physical layer framer outputs in other formats

suoto · Sep 19, 2020, 12:11 PM UTC

79a60e87b5de

dvb_fpga: imiprove README.

Anshul Makkar · Sep 18, 2020, 10:45 AM UTC

b3bb662aad3b

dvb-fpga: resolve the "unable to import VUnit and VUnitCLI" error while executing run.py.

Anshul Makkar · Sep 18, 2020, 10:40 AM UTC

7a4b40ecef8e

Passing DUT config via AXI file reader TID

suoto · Sep 6, 2020, 10:03 PM UTC

a9a0524df71f

Preferring frame type over frame length

suoto · Sep 4, 2020, 3:10 PM UTC

c7a3baba611e

Writing PL framer output to file

suoto · Sep 3, 2020, 1:39 PM UTC

2f5079074d45

Added resource usage to README

suoto · Sep 2, 2020, 9:22 PM UTC

97db7381b0ac

Using fancy icons :)

Andre Souto · Aug 31, 2020, 10:24 AM UTC

b09b2d8d8364

Parameters weren't being passed to DVB-S2X modulator

suoto · Aug 31, 2020, 9:33 AM UTC

48bc1bea6b2b

Dumping GR's bit mapper output to a file

suoto · Aug 14, 2020, 7:34 PM UTC

a55ca75625f5

Reorganized axi_ldpc_table code to hopefully make it easier to follow

suoto · Aug 9, 2020, 12:03 AM UTC

c013e29c3ebc

Pipelined offset was using wrong table_length register

suoto · Aug 8, 2020, 11:48 PM UTC

2fa8523ea290

Changed clk for Vivado build from 250 to 333 MHz

suoto · Aug 8, 2020, 10:41 PM UTC

5ad1f955be9a

File had manual changes, adding the auto generated

suoto · Aug 8, 2020, 3:15 PM UTC

514f3f01aadd