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dvb_fpga

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Commit history

Commits included in published releases. Unpublished intermediate commits are private. Showing matches from the latest 100 commits ending at this release.

Cleaning up

suoto · Jan 31, 2021, 12:19 PM UTC

eef01f0e1253

Moved endianess swap to plframe header testbench; working around some GHDL stuff

suoto · Jan 31, 2021, 11:49 AM UTC

14524b54d3d4

Fixed failing header values

suoto · Jan 31, 2021, 11:21 AM UTC

7fc6bc8cdd0b

WIP - some headers are OK, many still wrong

suoto · Jan 30, 2021, 11:45 PM UTC

efc324094384

Real/fixed point/signed stuff seemingly OK

suoto · Jan 27, 2021, 1:47 PM UTC

b90d7b48e268

Cleaning up plframe header code

suoto · Jan 24, 2021, 11:55 AM UTC

023c2631e8ed

plheader/testbench: dummy success for testbench.

Anshul Makkar · Jan 25, 2021, 1:13 PM UTC

98766308bab0

plheader: fix code and testbench.

Anshul Makkar · Jan 25, 2021, 12:37 PM UTC

26fb261137fc

testbench/plheader: resolve compilation issue.

Anshul Makkar · Jan 25, 2021, 12:09 PM UTC

0ed64cf37270

testbench/plheader: code improvement.

Anshul Makkar · Jan 22, 2021, 12:38 PM UTC

8d964280feb0

testbench/plheader: add testbench for plheader.

Anshul Makkar · Jan 21, 2021, 6:03 PM UTC

796b44c7194c

dvb_fpga/plheader: address review comments.

Anshul Makkar · Jan 21, 2021, 12:33 PM UTC

056a6c55bfe7

updated to fpga_cores latest

suoto · Jan 2, 2021, 11:38 AM UTC

fb5a28b4d2b0

Formatting code, adding FIXMEs with questions

suoto · Jan 1, 2021, 6:18 PM UTC

d7abe1515a69

dvb_fpga/plheader: uncomment plheader_pkg code to check for CI errors.

Anshul Makkar · Dec 31, 2020, 3:14 PM UTC

341ed0241ff1

dvb_fpga/plheader: uncommenting code to find CI error.

Anshul Makkar · Dec 31, 2020, 3:08 PM UTC

91dece3f05e6

dvb_fpga/plheader: fix compiilation issue.

Anshul Makkar · Dec 31, 2020, 2:50 PM UTC

449da0791858

dvb_fpga/plheader: add code for plheader insertion and synthesis.

Anshul Makkar · Dec 31, 2020, 2:47 PM UTC

d12faab3a930

Working around a GHDL issue that was causing Yosys to fail

suoto · Nov 15, 2020, 8:28 PM UTC

3bfc18a07704

Reworked github actions files

suoto · Nov 15, 2020, 8:09 PM UTC

303a4298a344

Merge pull request #8 from phase4ground/plinsert

Andre Souto · Oct 27, 2020, 11:31 AM UTC

8a0f085a10c5

dvb_fpga: black formatting.

Anshul Makkar · Sep 21, 2020, 11:00 AM UTC

a962810a37bc

dvb_fpga: resolve formatting bug.

Anshul Makkar · Sep 21, 2020, 10:59 AM UTC

4cda7a7f99c8

Update README.md

anshul makkar · Sep 21, 2020, 10:54 AM UTC

45e0587d081d

Update run.py

anshul makkar · Sep 21, 2020, 10:53 AM UTC

dae02914504d

Dumping fixed point modulator's output

suoto · Sep 20, 2020, 1:34 PM UTC

095a4274e96d

Also dumping of physical layer framer w pilots off

suoto · Sep 19, 2020, 4:39 PM UTC

8ead86281e6d

Dumping physical layer framer outputs in other formats

suoto · Sep 19, 2020, 12:11 PM UTC

79a60e87b5de

dvb_fpga: imiprove README.

Anshul Makkar · Sep 18, 2020, 10:45 AM UTC

b3bb662aad3b

dvb-fpga: resolve the "unable to import VUnit and VUnitCLI" error while executing run.py.

Anshul Makkar · Sep 18, 2020, 10:40 AM UTC

7a4b40ecef8e

Passing DUT config via AXI file reader TID

suoto · Sep 6, 2020, 10:03 PM UTC

a9a0524df71f

Preferring frame type over frame length

suoto · Sep 4, 2020, 3:10 PM UTC

c7a3baba611e

Writing PL framer output to file

suoto · Sep 3, 2020, 1:39 PM UTC

2f5079074d45

Added resource usage to README

suoto · Sep 2, 2020, 9:22 PM UTC

97db7381b0ac

Using fancy icons :)

Andre Souto · Aug 31, 2020, 10:24 AM UTC

b09b2d8d8364

Parameters weren't being passed to DVB-S2X modulator

suoto · Aug 31, 2020, 9:33 AM UTC

48bc1bea6b2b

Dumping GR's bit mapper output to a file

suoto · Aug 14, 2020, 7:34 PM UTC

a55ca75625f5

Reorganized axi_ldpc_table code to hopefully make it easier to follow

suoto · Aug 9, 2020, 12:03 AM UTC

c013e29c3ebc

Pipelined offset was using wrong table_length register

suoto · Aug 8, 2020, 11:48 PM UTC

2fa8523ea290

Changed clk for Vivado build from 250 to 333 MHz

suoto · Aug 8, 2020, 10:41 PM UTC

5ad1f955be9a

File had manual changes, adding the auto generated

suoto · Aug 8, 2020, 3:15 PM UTC

514f3f01aadd

Updating README

suoto · Aug 8, 2020, 3:14 PM UTC

6c6ae564a7d9

Renamed the run, we're not using Modelsim

suoto · Aug 8, 2020, 3:00 PM UTC

f7b07a85d1a2

Removed bit interleaver test with data width=1

suoto · Aug 7, 2020, 9:06 PM UTC

4a8919f2ad74

Config was not being written properly to axi_ldpc_table

suoto · Aug 7, 2020, 9:05 PM UTC

cd1ad7b82c80

Fixed some corner cases; creating ldpc tables in text for debug

suoto · Aug 7, 2020, 5:41 PM UTC

6d9418de62d4

Preferring get_field over extract

suoto · Aug 6, 2020, 11:24 PM UTC

3afe0e53f537

Constraining clk to 250 MHz on Vivado

suoto · Aug 5, 2020, 8:57 AM UTC

17c75eab34dd

Using fpga_cores.rom_inference, fixes on the axi_ldpc_table

suoto · Aug 5, 2020, 8:05 AM UTC

fd32b485cf4e

WIP - adding axi_ldpc_table and tb

suoto · Aug 1, 2020, 1:28 PM UTC

39c83c8a04bc

Documenting LDPC tables a bit

suoto · Jul 27, 2020, 9:14 PM UTC

94dc353c9e26

Simplified bit interleaver RAM addr scheme

suoto · Jul 26, 2020, 10:05 PM UTC

c42279cb4c1d

Running less DVB tx TB configs; fixing typos, code style

suoto · Jul 26, 2020, 6:31 PM UTC

7081d5616151

Encoding DVB parameters now return X's when value is not_set

suoto · Jul 26, 2020, 6:30 PM UTC

393738812c03

Fixed incorrect sampling of CRC frame length

suoto · Jul 26, 2020, 6:28 PM UTC

743e09972dae

Fix for issue #7 AXI bit interleaver reads invalid AXI tdata

suoto · Jul 4, 2020, 11:09 PM UTC

b5df4712712d

Working around Vivado/GHDL incompatibilities

suoto · Jun 20, 2020, 9:22 PM UTC

9df0746043e9

Merging add_ldpc_encoder

suoto · Jun 20, 2020, 7:40 PM UTC

2b2fb6f3f9e0

Merge pull request #6 from phase4ground/local-testing

Andre Souto · Jun 17, 2020, 1:29 PM UTC

226683da08be

gnuradio_data/Makefile: fix compilation error.

Anshul Makkar · Jun 17, 2020, 12:26 PM UTC

c1553085fe8a

dvbs2_tx needs LDPC before actually having a testbench

suoto · Feb 15, 2020, 11:04 PM UTC

082540ca1d31

Added dvbs2_tx and Yosys CI runs (fixes #4)

suoto · Feb 15, 2020, 10:25 PM UTC

bb52e4fdb09f

Importing and using config_fifo.vhd inside bit interleaver

suoto · Feb 10, 2020, 10:18 PM UTC

fdb0bbf2051e

Unwrapping shifted data muxes (fixes #5)

suoto · Feb 10, 2020, 10:17 PM UTC

58c953f45eee

Style and code consistency changes

suoto · Feb 9, 2020, 11:06 PM UTC

fa62634f9d93

Adding -2008 flags to testbench files

suoto · Feb 9, 2020, 6:57 PM UTC

b380e9c364ec

Initial GHDL/Yosys script

suoto · Feb 9, 2020, 2:35 PM UTC

67fb1b28276b

Data width = 1 takes too long, run them on different sims

suoto · Feb 9, 2020, 1:29 PM UTC

b271e9c79572

Generating test data within the main test runner

suoto · Feb 9, 2020, 1:11 PM UTC

ef6ef0c8bee4

Merge docker entry commands to the run test script itself

suoto · Feb 9, 2020, 12:22 PM UTC

5a9950cb5451

Fixing GNU Radio version on Dockerfile

suoto · Feb 8, 2020, 11:11 PM UTC

835ac9f19f50

Reduced the path's string size

suoto · Feb 8, 2020, 10:21 PM UTC

dbb3f61a88fe

Fixed some issues, but still not usable

suoto · Feb 8, 2020, 10:20 PM UTC

7aa12c443699

Updated README, consolidated tests to reduce run time

suoto · Feb 8, 2020, 10:19 PM UTC

e90547511cd0

Tweaked test timeouts and verbosity

suoto · Feb 8, 2020, 9:17 PM UTC

c77b877f43ac

Tweaked run script

suoto · Feb 8, 2020, 9:16 PM UTC

77db9f9205d1

File reader should now handle any data ratio

suoto · Feb 8, 2020, 9:12 PM UTC

00abfe5d3d49

Fixed typo -- shift registers are obviously not sh*t

suoto · Feb 8, 2020, 3:11 PM UTC

8047c099a7b8

temporary -- works..??

suoto · Feb 6, 2020, 10:13 PM UTC

f7bafc8e4ee7

Adjusted position of blocks

suoto · Feb 3, 2020, 9:48 PM UTC

956f76e949d1

Style fixes

suoto · Jan 29, 2020, 8:27 PM UTC

4346f23655f7

Working around GHDL out of bounds error

suoto · Jan 29, 2020, 8:27 PM UTC

78d6427e8ead

Preferring FIFO instead of stream adapter for the config FIFO

suoto · Jan 29, 2020, 8:26 PM UTC

803e1cf97bc7

Fixed conditions for wr_full to be asserted

suoto · Jan 29, 2020, 8:26 PM UTC

68aed94d76ca

Added baseband scrambler

suoto · Jan 28, 2020, 11:04 AM UTC

33c020107cf5

Separating input/reference file pair on a new record

suoto · Jan 28, 2020, 12:26 AM UTC

3b58dffcde2d

Updating README.md

suoto · Jan 27, 2020, 10:35 AM UTC

05104f70d429

Starting longer tests first to reduce overall test run time

suoto · Jan 27, 2020, 1:43 AM UTC

5d7c00be7bbb

Fixed some pylint warnings

suoto · Jan 27, 2020, 1:23 AM UTC

46e3792ba1b1

Using the correct Docker container

suoto · Jan 27, 2020, 1:05 AM UTC

30bb5ace9b17

Fixed bit interleaver, all tests now pass; Also updated README

suoto · Jan 27, 2020, 1:00 AM UTC

0bebb12e061d

temporary

suoto · Jan 22, 2020, 11:24 PM UTC

2b3de42cee76

Cleaning up

suoto · Jan 22, 2020, 2:59 PM UTC

38a4c8a29e56

Comparing to max cnt value for better timing

suoto · Jan 22, 2020, 2:58 PM UTC

2168413a208f

Updated README.md

suoto · Jan 22, 2020, 12:01 PM UTC

1abf8cda1f09

Fixed most failing cases for the bit interleaver code rate 3/5

suoto · Jan 22, 2020, 11:02 AM UTC

fb98ae7856ce

Fixed AXI file compare test

suoto · Jan 21, 2020, 7:07 PM UTC

d0c44076d62e

cleaning up

suoto · Jan 21, 2020, 5:12 PM UTC

2deb310a91f6

Tweaked stuff to allow ModelSim or GHDL

suoto · Jan 21, 2020, 4:49 PM UTC

b375906018a9

Adding VHDL version of skidbuffer.v (closes #3)

suoto · Jan 21, 2020, 3:02 PM UTC

703f14282792