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dvb_fpga

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Design files

suotoReplacing polyphase filter verilog files with VHDcd79fdeb8

Name	Storage	Size
.. / Parent directory
ldpc_table_FECFRAME_NORMAL_C1_2.csv	Git	2.2 KB
ldpc_table_FECFRAME_NORMAL_C1_3.csv	Git	2.0 KB
ldpc_table_FECFRAME_NORMAL_C1_4.csv	Git	1.5 KB
ldpc_table_FECFRAME_NORMAL_C2_3.csv	Git	2.3 KB
ldpc_table_FECFRAME_NORMAL_C2_5.csv	Git	2.4 KB
ldpc_table_FECFRAME_NORMAL_C3_4.csv	Git	2.5 KB
ldpc_table_FECFRAME_NORMAL_C3_5.csv	Git	3.3 KB
ldpc_table_FECFRAME_NORMAL_C4_5.csv	Git	2.5 KB
ldpc_table_FECFRAME_NORMAL_C5_6.csv	Git	2.6 KB
ldpc_table_FECFRAME_NORMAL_C8_9.csv	Git	2.0 KB
ldpc_table_FECFRAME_NORMAL_C9_10.csv	Git	2.0 KB
ldpc_table_FECFRAME_SHORT_C1_2.csv	Git	367 B
ldpc_table_FECFRAME_SHORT_C1_3.csv	Git	454 B
ldpc_table_FECFRAME_SHORT_C1_4.csv	Git	330 B
ldpc_table_FECFRAME_SHORT_C2_3.csv	Git	499 B
ldpc_table_FECFRAME_SHORT_C2_5.csv	Git	528 B
ldpc_table_FECFRAME_SHORT_C3_4.csv	Git	432 B
ldpc_table_FECFRAME_SHORT_C3_5.csv	Git	745 B
ldpc_table_FECFRAME_SHORT_C4_5.csv	Git	397 B
ldpc_table_FECFRAME_SHORT_C5_6.csv	Git	456 B
ldpc_table_FECFRAME_SHORT_C8_9.csv	Git	460 B

Name	Storage	Size
.. / Parent directory
ldpc_table_FECFRAME_NORMAL_C1_2.csv	Git	2.2 KB
ldpc_table_FECFRAME_NORMAL_C1_3.csv	Git	2.0 KB
ldpc_table_FECFRAME_NORMAL_C1_4.csv	Git	1.5 KB
ldpc_table_FECFRAME_NORMAL_C2_3.csv