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dvb_fpga

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Design files

Name	Storage	Size
.. / Parent directory
ldpc	Directory	—
Dockerfile	Git	1.2 KB
get_bch_column_data.py	Git	2.6 KB
ldpc_tables_to_ram.py	Git	14.1 KB

suotoReplacing polyphase filter verilog files with VHDcd79fdeb8

Name	Storage	Size
.. / Parent directory
ldpc	Directory	—
Dockerfile	Git	1.2 KB
get_bch_column_data.py	Git	2.6 KB
ldpc_tables_to_ram.py	Git	14.1 KB
run_synth.sh	Git	2.0 KB
run_tests.sh	Git	1.8 KB
system_architecture.png	Git	142.7 KB