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  <title id="title">Continuous one-bit-stream binary32 divider architecture</title>
  <desc id="desc">Two raw binary32 input streams split once into significand, exponent, and sign paths. A fixed significand graph uses a reciprocal seed, three serial multipliers, correction, and round-to-nearest ties-to-even. The three paths meet only in the final binary32 pack.</desc>
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  <text class="caption" x="600" y="45">Raw binary32 at the boundaries; one-bit arithmetic inside</text>

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  <text class="label" x="122" y="125">A / B input</text>
  <text class="detail" x="122" y="157">32 bits LSB-first</text>
  <text class="detail" x="122" y="183">II = 32 clocks</text>

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  <text class="label" x="360" y="126">Unpack once</text>
  <text class="detail" x="360" y="158">significand</text>
  <text class="detail" x="360" y="183">exponent / sign</text>

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  <text class="label" x="622" y="108">14-digit seed</text>
  <text class="detail" x="622" y="141">2^37 = Q x B + P</text>
  <text class="detail" x="622" y="169">non-restoring recurrence</text>

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  <text class="label" x="890" y="108">Q x P</text>
  <text class="detail" x="890" y="140">serial multiply 1</text>
  <text class="detail" x="890" y="168">form X1</text>

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  <text class="label" x="897" y="257">A' x X1</text>
  <text class="detail" x="897" y="288">serial multiply 2</text>
  <text class="detail" x="897" y="312">initial q0</text>

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  <text class="label" x="615" y="257">q0 x B</text>
  <text class="detail" x="615" y="288">serial multiply 3</text>
  <text class="detail" x="615" y="312">low 32 bits only</text>

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  <text class="label" x="345" y="257">Correct + round</text>
  <text class="detail" x="345" y="288">exact residual</text>
  <text class="detail" x="345" y="312">RNE ties-to-even</text>

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  <text class="label" x="605" y="418">Exponent stream</text>
  <text class="detail" x="605" y="447">Ea - Eb + 127 - adj</text>

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  <text class="label" x="605" y="533">Sign stream</text>
  <text class="detail" x="605" y="562">one XOR + delay</text>

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  <text class="label" x="895" y="414">Pack once</text>
  <text class="detail" x="895" y="448">U31 boundary</text>
  <text class="detail" x="895" y="480">fixed 1,024-clock</text>
  <text class="detail" x="895" y="507">input-to-output</text>
  <text class="detail" x="895" y="534">latency</text>

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  <text class="label" x="1110" y="452">Result</text>
  <text class="detail" x="1110" y="483">32 bits</text>
  <text class="detail" x="1110" y="508">LSB-first</text>

  <text class="detail" x="600" y="625">After fill: one complete division every 32 clocks = 6,750,000 divisions/s at 216 MHz</text>
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