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<title>FPGA Systems, RF, Ethernet RTL & Reconfigurable Hardware | Brian Greenforest</title>
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<header><h1 class="page-title">FPGA Systems From Pins To Bitstreams</h1></header>
<section class="abstract">
<p class="lead">Complete FPGA systems emerge when pins, protocols, clocks, arithmetic, and configuration become one design.</p>
<p>This work follows each machine through pin-level signal behavior, packet parsing, clocking, arithmetic schedules, configuration transport, device primitives, open toolchains, and the Linux or browser surface that controls it.</p>
<div class="cta-row" role="group" aria-label="Explore Brian Greenforest's FPGA systems">
<a class="cta-link" href="/serial-binary32-divider/">Binary32 divider</a>
<a class="cta-link" href="how-much-radio-do-you-actually-need.html">RF receiver</a>
<a class="cta-link" href="/fpga-radio-lab/106-channel-one-pin-transmitter.html">106-channel one-pin TX</a>
<a class="cta-link" href="ethernet-udp-ice40-reprogrammer.html">Ethernet reprogrammer</a>
<a class="cta-link" href="physical-mux-tiles/">Physical MUX tiles</a>
<a class="cta-link" href="/fpga-verilog/">Learn FPGA And Verilog</a>
<a class="cta-link" href="contact.html">Discuss FPGA work</a>
</div>
</section>
<figure class="inspectable-image inspectable-image--fit">
<a href="/fpga-radio-lab/106-channel-one-pin-transmitter.html">
<img src="fpga-radio-lab/media/106-channel-one-pin-transmitter-physical-spectrum.png" width="2880" height="1980" loading="eager" decoding="async" alt="Physical spectrum of 106 independently moving FPGA RF channels across the complete 222 to 225 megahertz grid">
</a>
<figcaption>One HX8K creates 106 concurrent FM lanes on a 120-slot grid, reduces their complex sum through continuous bit-serial arithmetic, and switches the complete 3 MHz band through N16.</figcaption>
</figure>
<main>
<section>
<h2>The System Lives Where The Blocks Meet</h2>
<p>An FPGA joins electrical behavior, clocks, packet structure, state, routing, and configuration in one programmable machine. The decisive engineering happens at those joins.</p>
<p>The systems here span Lattice iCE40 and Xilinx 7-series hardware, Verilog and SystemVerilog, vendor primitives, Yosys-based toolchains, raw network framing, RF threshold crossings, and direct reconfiguration of one FPGA by another.</p>
<p>For a first encounter with FPGAs, begin with <a href="/fpga-verilog/">All Things All The Time: FPGA And Verilog From First Principles</a>. It builds upward from Boolean logic, LUTs, and flip-flops through Verilog, simulation, synthesis, placement, routing, and a programmed iCE40 board.</p>
</section>
<section>
<h2>FPGA Paths From Signal To System</h2>
<div class="capability-grid">
<article class="capability-card">
<a href="/wi-fi-through-one-fpga-input.html"><img src="/social-previews/wi-fi-through-one-fpga-input.png" width="1200" height="630" loading="lazy" decoding="async" alt="Wi-Fi through one FPGA input: 129-byte received beacon and zero repaired bits"></a>
<p class="eyebrow">Wideband front end meets Wi-Fi</p>
<h3><a href="/wi-fi-through-one-fpga-input.html">Wi-Fi Through One FPGA Input</a></h3>
<p>2.437 GHz downconverted to a 67 MHz IF, autonomous threshold control and a complete beacon recovered on the PC. No external LNA. Download the exact packet, PCAP, decoder and measured-data PNG.</p>
</article>
<article class="capability-card">
<a href="/e310-wpa2-access-point/"><img src="/e310-wpa2-access-point/cover.png" width="1200" height="630" loading="lazy" decoding="async" alt="Why Wi-Fi needs a real-time radio: received frame, 10 microsecond gap, acknowledgment"></a>
<p class="eyebrow">Radio through application</p>
<h3><a href="/e310-wpa2-access-point/">Why Wi-Fi Needs a Real-Time Radio</a></h3>
<p>From Barker-spread I/Q to an encrypted HTTP page: the 10 µs reply path, a zero-DSP serial detector, every joining exchange, CCMP byte construction and the C++ network stack. Field maps, worked arithmetic, complete source and build scripts.</p>
</article>
<article class="capability-card">
<a href="/forty-gigahertz-should-be-a-building-block.html"><img src="/social-previews/forty-gigahertz-should-be-a-building-block.png" width="1200" height="630" loading="lazy" decoding="async" alt="Forty Gigahertz Should Be a Building Block"></a>
<h3><a href="/forty-gigahertz-should-be-a-building-block.html">Forty Gigahertz Should Be a Building Block</a></h3>
<p>Compare purchasable ADCs, scopes, raw PLL binary receivers and microwave mixers. Follow a two-core up/downconverter and four-core Weaver receiver from one RF input to a sampled IF.</p>
</article>
<article id="rf-systems" class="capability-card">
<a href="how-much-radio-do-you-actually-need.html"><img src="one-pin-RF/images/one-pin-fpga-fm-receiver-illustration.png" width="1672" height="941" loading="lazy" decoding="async" alt="Illustrated one-pin FPGA FM receiver path from thresholded RF to recovered audio"></a>
<p class="eyebrow">RF receive</p>
<h3><a href="how-much-radio-do-you-actually-need.html">One-Pin FPGA FM Receiver</a></h3>
<p>A thresholded RF stream enters one logical differential iCE40 input site. DDR decisions become I/Q bit lanes, DDS sign bits control four XOR-and-popcount terms, and a later I/Q cross product recovers FM phase movement before sigma-delta audio.</p>
<p><a href="one-pin-sdr-fpga-bias-control.html">The September 2026 receiver</a> adds FPGA-only bias regulation, full-band capture and numerical I/Q. Hear the actual no-external-LNA recording and download the complete source. The original article preserves the earlier analog-audio design.</p>
</article>
<article class="capability-card">
<a href="/fpga-radio-lab/106-channel-one-pin-transmitter.html"><img src="fpga-radio-lab/media/106-channel-one-pin-transmitter-physical-spectrum.png" width="2880" height="1980" loading="lazy" decoding="async" alt="Physical 120-slot spectrum with 106 occupied FPGA transmitter channels and 14 deliberate holes"></a>
<p class="eyebrow">RF transmit · 106 concurrent channels</p>
<h3><a href="/fpga-radio-lab/106-channel-one-pin-transmitter.html">106-Channel One-Pin FPGA Transmitter</a></h3>
<p>The HX8K implements 106 independent 24-bit phase engines, deterministic FM motion, twin 128-leaf bit-serial I/Q trees, signed sigma-delta conversion, and a 7.5 MHz complex rotation before four 216 MHz phases converge on N16.</p>
<p>The complete SystemVerilog, support RTL, constraints, build, volatile-SRAM loader, hardware guide, and ready-to-load image are MIT licensed. <a href="/fpga-radio-lab/106-channel-one-pin-transmitter.html">Own the architecture and build it.</a></p>
</article>
<article class="capability-card">
<a href="ethernet-udp-ice40-reprogrammer.html"><img src="ethernet-udp-ice40-reprogrammer/images/port-of-edmonds-working-reprogrammer-waveform-2020.png" width="785" height="1050" loading="lazy" decoding="async" alt="January 2020 working-reprogrammer waveform with green digital traces"></a>
<p class="eyebrow">Network and configuration</p>
<h3><a href="ethernet-udp-ice40-reprogrammer.html">Ethernet To An Adjacent iCE40</a></h3>
<p>A 2020 multi-file system receives RMII Ethernet, answers ARP, ingests a fixed-layout bitstream through IPv4/UDP, stores it in FPGA RAM, and controls an adjacent iCE40LP384 configuration interface directly.</p>
<p>The Linux sender combines UDP, epoll, XCB, EGL, and GLES2 in one control shell.</p>
</article>
<article class="capability-card">
<p class="eyebrow">Arithmetic scheduling</p>
<h3><a href="serial_multiplier/">64-Bit Continuous Serial Multiplier</a></h3>
<p>The SystemVerilog core produces one low 64-bit product every 64 clocks at 216 MHz: 3.375 million products per second from 254 LUT4s and 635 flip-flops.</p>
<p>Twelve independent cores fit the HX8K and deliver 40.5 million products per second. The article publishes the RTL, build, utilization, host verifier, and physical run data.</p>
</article>
<article class="capability-card">
<p class="eyebrow">Binary32 arithmetic</p>
<h3><a href="/serial-binary32-divider/">Binary32 Serial Divider: 6.75 Million Divisions/s</a></h3>
<p>Raw IEEE binary32 words cross the boundary LSB first while significands, exponents, and signs move through one-bit internal streams. A 216 MHz HX8K accepts a new finite-normal division every 32 clocks.</p>
<p>Three serial multipliers, eight add/subtract engines, and three comparators turn the continuous schedule into 6.75 million correctly rounded finite-normal divisions per second, with open RTL and complete rebuild files.</p>
</article>
<article class="capability-card">
<p class="eyebrow">Tangible logic</p>
<h3><a href="physical-mux-tiles/">Physical MUX Tiles For STEM EE</a></h3>
<p>Input, constant, selector, route, and intersection PCB variants turn circuit role, orientation, and topology into objects that learners can assemble and change by hand.</p>
<p>This physical teaching alphabet carries the logic of MUXes and LUTs out of diagrams and into palm-scale compositions.</p>
</article>
<article class="capability-card">
<p class="eyebrow">Spatial reconfiguration</p>
<h3><a href="cartilage/">Cartilage</a></h3>
<p>Cartilage organizes cells into locally coherent regions with owned ports, state, routing, and replacement. Its learning path runs from one MUX through LUTs, drivers, clock distribution, state, timing, metal, composition, and runtime instantiation in adjacent space.</p>
<p><a href="cartilage-core.html">Run Cartilage Core</a>, then follow the <a href="cartilage-reconfigurable-computing-roadmap.html">editor, simulator, ownership, and recovery roadmap</a>. The architecture invites funding, implementation partners, and contributors.</p>
</article>
</div>
</section>
<section>
<h2>Devices, Primitives, And Toolchains</h2>
<div class="article-fact-table" role="table" aria-label="FPGA devices, primitives, and tools represented in the public work">
<div class="article-fact-row" role="row"><div class="article-fact-key" role="cell">Lattice targets</div><div role="cell">iCE40 UP5K, HX4K/HX8K, and LP384 source, builds, radio paths, and configuration control</div></div>
<div class="article-fact-row" role="row"><div class="article-fact-key" role="cell">Xilinx target</div><div role="cell">Arty / 7-series Ethernet controller with an adjacent-device reprogrammer</div></div>
<div class="article-fact-row" role="row"><div class="article-fact-key" role="cell">HDL</div><div role="cell">Verilog and SystemVerilog with PLLs, global buffers, DDR input, RMII, RAM, CRC, and configuration-pin control</div></div>
<div class="article-fact-row" role="row"><div class="article-fact-key" role="cell">One-bit arithmetic</div><div role="cell">A 254-LUT4 64-bit low-product multiplier at 3.375M/s and a binary32 divider at 6.75M/s on the HX8K at 216 MHz</div></div>
<div class="article-fact-row" role="row"><div class="article-fact-key" role="cell">Open toolchains</div><div role="cell">Yosys, nextpnr, IceStorm, arachne-pnr, IcePack, Verilator, and Logisim</div></div>
<div class="article-fact-row" role="row"><div class="article-fact-key" role="cell">Host systems</div><div role="cell">Linux UDP and epoll, XCB events, EGL/GLES2, raw WebGL/GLSL, and browser-visible tests</div></div>
</div>
</section>
<section>
<h2>One Engineer Can Follow The Whole Computation</h2>
<p class="lead">The useful abstraction ends where it stops matching the machine.</p>
<p>The right intervention may take the form of an arithmetic schedule, an FPGA input threshold at the front of a receiver, an ARP response and bitstream path with no CPU in the datapath, a configuration port between devices, or a circuit alphabet that a learner can hold.</p>
<p>That cross-layer range turns hardware, software, protocols, and physical behavior back into one tractable system—the point where difficult product and research problems often yield.</p>
</section>
<section class="traction-panel">
<h2>Bring The FPGA Problem That Does Not Fit The Usual Stack</h2>
<p>Start with an RTL path, signal interface, timing problem, packet boundary, reconfiguration mechanism, teaching instrument, or architecture. Together, we can turn it into a machine that a team can run, inspect, and develop.</p>
<div class="cta-row">
<a class="cta-link" href="technology-research-and-consulting.html">Commission FPGA R&D</a>
<a class="cta-link" href="proof-and-artifacts.html">Explore working systems</a>
<a class="cta-link" href="mailto:brian@solidstatepros.com?subject=FPGA%20systems%20inquiry%20for%20Greenforest%20I%2FO">Email an FPGA inquiry</a>
</div>
</section>
</main>
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<p>Read next:</p>
<a href="ethernet-udp-ice40-reprogrammer.html">Ethernet To An Adjacent iCE40</a>
<p>Follow the 2020 Verilog, configuration interface, and Linux host controller from packet to programmed device.</p>
<p>More:</p>
<a href="physical-mux-tiles/">Physical MUX Tiles For STEM EE</a>
<p>Build the roles of reconfigurable logic from a hand-assemblable PCB alphabet.</p>
<a href="/">Back to greenforest.io</a>
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