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<title>Brian Greenforest | FPGA, Radio, WebGL & Cartilage Inventions</title>
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<header>Greenforest I/O</header>
<h1 class="tagline">Working inventions that open new ways to compute, communicate, and build.</h1>
<main>
<section class="abstract">
<p class="lead">One FPGA pin synthesizes 106 independently moving RF channels across 3 MHz. One-bit arithmetic produces 3.375 million 64-bit products or 6.75 million binary32 quotients per second on an HX8K. Cartilage installs and replaces spatial circuit regions. Raw WebGL turns a browser texture into a visible computing machine.</p>
<p>Greenforest I/O develops the mechanism itself—circuit, shader, fabric, RTL, board, or physical process—so an engineer can run it, understand it, and carry it into a product or research program.</p>
<div class="cta-row" role="group" aria-label="Start with Brian Greenforest's work">
<a class="cta-link" href="/serial-binary32-divider/">Divide at 6.75M/s</a>
<a class="cta-link" href="serial_multiplier/">Stream the multiplier</a>
<a class="cta-link" href="/fpga-radio-lab/106-channel-one-pin-transmitter.html">Build the 106-channel transmitter</a>
<a class="cta-link" href="webgl-glsl-computing.html">Run raw WebGL compute</a>
<a class="cta-link" href="cartilage/">Build upward to Cartilage</a>
<a class="cta-link" href="/cartilage-multiplier-demo/">Run the open Cartilage multiplier</a>
<a class="cta-link" href="/cartilage-simple-canvas-at-home.html">Download Cartilage for offline use</a>
<a class="cta-link" href="technology-research-and-consulting.html">Commission hard R&D</a>
</div>
</section>
<section id="thought-meltdown">
<h2><a href="/thought-meltdown.html">Thought Meltdown: Our Lives Are Too Short for This Mess</a></h2>
<p>Unfinished thoughts become systems we can barely understand. Overengineering, corporate compromises, and AI can keep the pile growing. We need the courage to recover the essential mechanism and start again.</p>
<p><a href="/thought-meltdown.html">Read the essay on clarity, cleanup, and the things we leave for one another</a></p>
</section>
<section id="measurement-access">
<h2><a href="/forty-gigahertz-should-be-a-building-block.html">Forty Gigahertz Should Be a Building Block</a></h2>
<p>What can a builder actually buy to measure one microwave signal? Compare raw ADCs, 200 GS/s oscilloscopes, reference-clocked binary receivers, and $36 dual or $72 Weaver-quad MDB-44H+ conversion.</p>
<p><a href="/forty-gigahertz-should-be-a-building-block.html">Follow the signal paths and compare the priced parts</a></p>
</section>
<section id="one-pin-wifi-update"><h2><a href="wi-fi-through-one-fpga-input.html">Wi-Fi Through One FPGA Input</a></h2><p>A complete 129-byte Wi-Fi beacon, received through the wideband FPGA front end with no external LNA. Follow the E310 story into a new receive path; inspect the exact packet, checksums, measured data and open-source decoder.</p></section>
<section id="one-pin-sdr-update"><h2><a href="one-pin-sdr-fpga-bias-control.html">One FPGA Input Captures DC–204 MHz—and Controls Its Own Bias</a></h2><p>Explore a simultaneous DC–204 MHz spectrum and listen to the actual 106.5 MHz recording, both received without an external LNA. The FPGA regulates its bias capacitor and exports RF decisions and numerical I/Q. <a href="one-pin-sdr-fpga-bias-control.html">Play the clip and download the complete Verilog, circuit, controller and host code.</a></p></section>
<section id="open-radio">
<h2>Why Wi-Fi Needs a Real-Time Radio</h2>
<p>Build the path from I/Q samples to an encrypted HTTP page: Barker correlation, bit-serial multiplication, the 10 µs ACK deadline, association, WPA2 keys, CCMP, DHCP, ARP and TCP. Includes byte layouts, arithmetic, state transitions, full source and build scripts.</p>
<p><a href="/e310-wpa2-access-point/">Read the implementation guide and download the C++ and RTL</a></p>
</section>
<section id="working-results">
<h2>Four Machines, Three Scales</h2>
<p>Two clock-by-clock arithmetic schedules, a GPU-wide state machine, and a recursively reconfigurable fabric expose the structure that conventional stacks hide.</p>
<div class="capability-grid">
<article class="capability-card">
<span class="eyebrow">Correctly rounded binary32</span>
<h3><a href="/serial-binary32-divider/">Binary32 Serial Divider: 6.75 Million Divisions/s</a></h3>
<p>Raw IEEE binary32 operands enter LSB first. Three serial multipliers, eight add/subtract engines, and three comparators carry significand, exponent, and sign through one-bit internal streams and accept another finite-normal division every 32 clocks at 216 MHz.</p>
<p><a href="/serial-binary32-divider/">Download the open RTL, rebuild files, utilization, and physical run</a></p>
</article>
<article class="capability-card">
<a href="serial_multiplier/"><img src="social-previews/serial_multiplier/index.png" width="1200" height="630" loading="eager" decoding="async" alt="Timing-focused preview of the bubbles-free bit-serial multiplier"></a>
<span class="eyebrow">Continuous arithmetic</span>
<h3><a href="serial_multiplier/">A 64-bit serial multiplier delivers 3.375 million products/s</a></h3>
<p>The 254-LUT4, 635-flip-flop SystemVerilog core accepts the next operand word every 64 clocks at 216 MHz. Twelve copies fit the HX8K and deliver 40.5 million low 64-bit products per second.</p>
<p><a href="serial_multiplier/">Download the RTL, build, utilization report, and physical results</a></p>
</article>
<article class="capability-card">
<a href="webgl-glsl-computing.html"><img src="cellular-automata-2019/thumbs/vortex.png" width="720" height="405" loading="eager" decoding="async" alt="A stateful WebGL cellular automaton rendered from packed texture state"></a>
<span class="eyebrow">Browser GPU machines</span>
<h3><a href="webgl-glsl-computing.html">Raw WebGL and GLSL turn textures into computing state</a></h3>
<p>Contexts, GLSL ES shaders, textures, framebuffers, packed state, ping-pong updates, and readback form the complete machine. Each browser call stays close enough to inspect, change, and teach from first principles.</p>
<p><a href="webgl-glsl-computing.html">Build the browser-to-GPU path</a></p>
</article>
<article class="capability-card capability-card-wide">
<a href="cartilage/"><img src="cartilage/logic-to-luts.svg" width="1200" height="675" loading="lazy" decoding="async" alt="Cartilage learning-path diagram from multiplexers through LUT1 to LUT6"></a>
<span class="eyebrow">Spatial reconfigurable architecture</span>
<h3><a href="cartilage/">Cartilage grows from one multiplexer into replaceable circuit regions</a></h3>
<p>Each Cartilage region owns ports, state, routing, and the path that replaces its interior. The learning path starts with Logisim and LUTs, then adds physical drive, distribution, statecharts, timing, wires, composition, and runtime installation in adjacent space.</p>
<p><a href="cartilage/">Build the eight-stage architecture</a> · <a href="/cartilage-simple-canvas-at-home.html">Take Cartilage home</a> · <a href="cartilage-circuit-workstation.html">Open the circuit workstation</a> · <a href="/cartilage-multiplier-demo/">Run the public multiplier</a> · <a href="cartilage-reconfigurable-computing-roadmap.html">Fund or join development</a></p>
</article>
</div>
</section>
<section id="fpga-systems">
<h2>One FPGA Practice Spans Signal, Protocol, Logic, And Configuration</h2>
<p class="lead">The same command of clocks, state, and physical pins connects radio, Ethernet, arithmetic, and runtime reconfiguration.</p>
<p>These systems receive and transmit RF, answer ARP in direct RTL, carry FPGA images through UDP, reprogram an adjacent iCE40, turn multiplexers into tangible tiles, and travel from Verilog through place-and-route to configured hardware. <a href="fpga-systems.html">Enter the complete FPGA systems map</a>.</p>
<div class="capability-grid">
<article class="capability-card">
<a href="/fpga-radio-lab/106-channel-one-pin-transmitter.html"><img src="fpga-radio-lab/media/106-channel-one-pin-transmitter-physical-spectrum.png" width="2880" height="1980" loading="lazy" decoding="async" alt="Physical spectrum of 106 independently moving FPGA RF channels across a 120-slot, 3 megahertz grid"></a>
<span class="eyebrow">RF transmit · 106 concurrent channels</span>
<h3><a href="/fpga-radio-lab/106-channel-one-pin-transmitter.html">One FPGA pin synthesizes 106 RF channels across 3 MHz</a></h3>
<p>The HX8K advances 106 independent 24-bit lane phases, reduces their live I/Q contributions through 254 bit-serial tree nodes, and turns the complete 4.5 MS/s complex band into four-phase RF timing on N16.</p>
<p><a href="/fpga-radio-lab/106-channel-one-pin-transmitter.html">Inspect every stage and download the complete MIT-licensed transmitter</a></p>
</article>
<article class="capability-card">
<a href="how-much-radio-do-you-actually-need.html"><img src="one-pin-RF/images/one-pin-fpga-fm-receiver-illustration.png" width="1672" height="941" loading="lazy" decoding="async" alt="Illustrated one-pin FPGA FM receiver path from thresholded RF to recovered audio"></a>
<span class="eyebrow">RF receive</span>
<h3><a href="one-pin-sdr-fpga-bias-control.html">One FPGA input captures wideband RF</a></h3>
<p>Simultaneous DC–204 MHz capture, clear FM audio and FPGA-only bias control, without an external LNA. Download the actual recordings, complete Verilog, circuits and host processing.</p>
<p><a href="one-pin-sdr-fpga-bias-control.html">Hear the latest recording and download the autonomous receiver</a> · <a href="how-much-radio-do-you-actually-need.html">Original design</a></p>
</article>
<article class="capability-card">
<a href="ethernet-udp-ice40-reprogrammer.html"><img src="social-previews/ethernet-udp-ice40-reprogrammer.png" width="1200" height="630" loading="lazy" decoding="async" alt="Preview for the Ethernet-to-iCE40 Verilog reprogrammer article"></a>
<span class="eyebrow">Network RTL and reconfiguration</span>
<h3><a href="ethernet-udp-ice40-reprogrammer.html">An Ethernet packet reprograms the FPGA next door</a></h3>
<p>The 2020 system receives RMII, answers ARP, ingests a fixed-layout IPv4/UDP bitstream into FPGA RAM, and directly configures a neighboring iCE40LP384. Its Linux sender joins UDP, epoll, XCB, EGL, and GLES2 into the host side of the path.</p>
<p><a href="ethernet-udp-ice40-reprogrammer.html">Follow all 14 source files from packet to bitstream</a></p>
</article>
<article class="capability-card capability-card-wide">
<a href="physical-mux-tiles/"><img src="physical-mux-tiles/media/assembly.webp" width="1440" height="1080" loading="lazy" decoding="async" alt="A palm-scale assembly of physical purple MUX, input, constant, route, and intersection PCB tiles"></a>
<span class="eyebrow">Tangible logic for electrical engineering</span>
<h3><a href="physical-mux-tiles/">A fabricated MUX-tile alphabet makes logic spatial</a></h3>
<p>PCB tiles give inputs, constants, selectors, routes, intersections, orientation, and topology a physical form that learners can assemble by hand. The system connects those pieces to Logisim, LUT1–LUT6, and FPGA logic, then carries them toward a powered teaching product.</p>
<p><a href="physical-mux-tiles/">See the assembled tiles and build the learning path</a></p>
</article>
</div>
</section>
<section id="value">
<h2>Open The Boundary That Controls The Product</h2>
<p class="lead">Inherited stacks often hide the exact timing, state, routing, or physical constraint that decides whether a new system can exist.</p>
<p>Greenforest I/O turns that hidden boundary into explicit machinery: a circuit schedule, shader pipeline, reconfigurable substrate, radio path, or fabrication process that a team can inspect and extend. This work creates leverage before convention hardens into an assumed law.</p>
</section>
<section id="work-with-me" class="traction-panel">
<h2>Bring The Boundary Everyone Else Treats As Fixed</h2>
<p>Strong projects include computation trapped behind a black box, arithmetic shaped incorrectly for its surrounding graph, opaque hardware/software interfaces, FPGA architectures that need a complete physical path, and process ideas that demand reasoning from physics back to working machinery.</p>
<p><strong>Ways to engage:</strong> funded R&D, research architecture, product development, implementation, technical due diligence, FPGA/WebGL/semiconductor/radio collaboration, fabrication or laboratory access, and an institutional home for Cartilage and active-device development.</p>
<div class="cta-row" role="group" aria-label="Work with Brian Greenforest">
<a class="cta-link" href="technology-research-and-consulting.html">Choose an engagement</a>
<a class="cta-link" href="proof-and-artifacts.html">Open the working systems</a>
<a class="cta-link" href="contact.html">Send the hard boundary</a>
</div>
</section>
<section id="other-work">
<h2>Research Programs And Essays Beyond Conventional Systems</h2>
<div class="entry">
<span class="label">Cultural critique · August 2026</span>
<a class="entry-title" href="encanto-removed-the-villain-now-remove-power.html">Encanto Removed the Villain. Now Remove Power.</a>
<p><em>Encanto</em> removes the villain and exposes a harder problem: love can become command. The essay follows that insight through family, school, work, human rights, refusal, and a world without masters.</p>
</div>
<div class="entry">
<span class="label">We Got It All Wrong · Series premiere</span>
<a class="entry-title" href="we-got-it-all-wrong.html">The Forest And The Right To Create</a>
<p>One finite human life deserves tools and education that expose how creation works. Watch the first episode and read the argument for moving people from constrained consumption into authorship.</p>
</div>
<div class="entry">
<span class="label">Company-scale problem map · 210 openings</span>
<a class="entry-title" href="210-problems-we-have-learned-to-call-normal.html">210 Problems We Have Learned To Call Normal</a>
<p>The map connects three company-sized layers: structurally bounded authority for agents and machines, live reconfigurable physical computation, and physical intelligence built from minimal apparatus. Each layer supports a focused subsidiary and a portfolio of products.</p>
</div>
<div class="entry">
<span class="label">Long-form collection · 53 essays</span>
<a class="entry-title" href="miscellanies/">Miscellanies</a>
<p>Fifty-three finished essays develop living circuits, self-reconfiguring machines, software and communication, physical models, mind and society, language, building, learning, and creative tools.</p>
</div>
<div class="entry">
<span class="label">Manufacturing program</span>
<a class="entry-title" href="the-missing-maker-fab.html">The Missing Maker Fab</a>
<p>The maker loop already produces boards, enclosures, firmware, and fixtures. The missing machine fabricates active devices with nonlinear gain, restoration, fanout, interconnect, and enough repeatability for useful logic at civic scale.</p>
</div>
<div class="entry">
<span class="label">Universal computing substrate</span>
<a class="entry-title" href="boolean-algebra-is-all-that-is-required.html">Boolean Algebra Is All That Is Required</a>
<p>The construction uses Boolean state and switching for application logic, ownership, configuration transport, timing, and recursive circuit replacement. <a href="mux-algebra.html">MUX Algebra</a> supplies the nested-selector derivation and all sixteen two-input functions.</p>
</div>
<div class="entry">
<span class="label">Transformer training from source</span>
<a class="entry-title" href="four-layer-tiny-transformer-training-run.html">Four-Layer Transformer Training Run</a>
<p>The complete run joins architecture, tokenizer, command, loss history, generated samples, and source through more than 50,000 training iterations.</p>
</div>
<div class="entry">
<span class="label">Procedural renderer</span>
<a class="entry-title" href="linkedin-archive/2025-08-19-cheap-pixelless-textures-with-2d-sdfs.html">Cheap Pixelless Textures With 2D SDFs</a>
<p>A self-contained scanline renderer uses UV-space signed-distance material tests and procedural geometry to construct a forest scene without ordinary bitmap texture art.</p>
</div>
</section>
<section id="evidence-trails">
<h2>Build From The Mechanisms</h2>
<div class="entry">
<span class="label">Downloadable offline Cartilage authoring</span>
<a class="entry-title" href="/cartilage-simple-canvas-at-home.html">Take Cartilage Home In One HTML File</a>
<p>Download the complete square-lattice authoring tool or the Rhombitrihex visual-language canvas, open either without an internet connection, build labeled circuits, and exchange circuit files through ordinary Open and Save controls.</p>
</div>
<div class="entry">
<span class="label">Open Cartilage multiplier and private workstation</span>
<a class="entry-title" href="cartilage-circuit-workstation.html">Run Cartilage In The Browser</a>
<p>Open the self-contained one-slot multiplier without an account, then request private access to edit, load, save, share, and follow the browser, Raspberry Pi, and FPGA streaming work.</p>
</div>
<div class="entry">
<span class="label">Cartilage in browser and RTL</span>
<a class="entry-title" href="cartilage-core.html">Cartilage Core in WebGL and SystemVerilog</a>
<p>Run one exact 252-bit installation through the compact WebGL1 model and local-clocked SystemVerilog RTL, then follow the architecture paper and Verilator testbench into the mechanism.</p>
</div>
<div class="entry">
<span class="label">Browser GPU lineage</span>
<a class="entry-title" href="from-the-ground-up/">WebGL And Computation From First Principles</a>
<p>Create the context, compile the shaders, allocate textures, execute through a framebuffer, and watch state become logic and addition directly on the GPU.</p>
</div>
<div class="entry">
<span class="label">Stateful local-rule machines</span>
<a class="entry-title" href="cellular-automata-2019/">Cellular Automata Experiments, 2019–2021</a>
<p>Local rules move packed state through reversible routes, conservative dynamics, machine-like flows, and the architectural path that produced Cartilage.</p>
</div>
<div class="entry">
<span class="label">Technical history</span>
<a class="entry-title" href="shader-before-gpu-renderman-ai-hardware.html">Programmable Shaders Before The GPU</a>
<p>RenderMan shading leads through real-time shader languages, Brook, CUDA, AlexNet, and mixed-precision matrix engines—a direct technical lineage from programmable color to AI arithmetic.</p>
</div>
<div class="entry">
<span class="label">135 dated technical essays</span>
<a class="entry-title" href="linkedin-archive/">LinkedIn Publication Index</a>
<p>Technical arguments, invention programs, collaboration openings, and original source records form a dated map from 2018 through 2026.</p>
</div>
</section>
<section id="open-research-threads">
<h2>Research Programs Ready For A Lab</h2>
<p><strong>Magnetics</strong> pursues amplification and circuit behavior beyond semiconductor fabrication. <strong>Learning machinery</strong> wires gradients directly through primitive operations. <strong>Fabrication</strong> brings active substrates within reach of civic-scale builders.</p>
<p>The <a href="the-missing-maker-fab.html">maker-fab program</a> and <a href="wafer-diced-smart-dust-substrate.html">wafer-diced substrate architecture</a> connect the material path to products. <a href="contact.html">Bring laboratory access, development capital, a customer problem, or an institutional home</a>.</p>
</section>
</main>
<footer>
<p>Brian Greenforest develops Greenforest I/O in connection with <a href="https://www.solidstatepros.com/" target="_blank" rel="noopener">Solid State Pros LLC</a>.</p>
<p><a href="about-greenforest.html">Meet the systems builder</a> | <a href="technology-research-and-consulting.html">Commission R&D</a> | <a href="proof-and-artifacts.html">Open the working systems</a> | <a href="fpga-systems.html">FPGA systems</a> | <a href="cartilage/">Cartilage</a> | <a href="webgl-glsl-computing.html">WebGL & GLSL</a> | <a href="contact.html">Start a conversation</a> | <a href="faq.html">Questions</a> | <a href="privacy.html">Privacy</a> | <a href="terms.html">Terms</a></p>
<p>© Brian Greenforest 2019-2026</p>
<p><a href="https://www.linkedin.com/in/briangreenforest" target="_blank" rel="noopener">Connect on LinkedIn</a></p>
<p><a href="site-map.html">Site Map</a></p>
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