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VexRiscv

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Design files

Charles Paponbetter travis timings travis job naming reduce verilator cache size Fix dcache test timeout travis cleaning travis wip verilator wip fix java 10 compilation Travis wip travis rework3b0f2e955

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Source

PROJ_NAME=emulator
DEBUG=no
MULDIV=no
COMPRESSED=no
STANDALONE = ..


SRCS = 	$(wildcard src/*.c) \
		$(wildcard src/*.cpp)  \
		$(wildcard src/*.S)


LDSCRIPT = ${STANDALONE}/common/ram.ld

include ${STANDALONE}/common/riscv64-unknown-elf.mk
include ${STANDALONE}/common/standalone.mk

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