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VexRiscv

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Merge branch 'linux' into linuxDev

Charles Papon · Apr 19, 2019, 7:12 PM UTC

06e63252e48d

#60 Added automated linux regression in travis Fix DBusCached plugin access sharing for the MMU deadlock when exception is in the decode stage Fix IBusSimplePlugin issues with used with non regular configs + MMU Bring back the LinuxGen config into a light one

Charles Papon · Apr 19, 2019, 3:35 PM UTC

e47b76fa6779

Make regression sim great again

Charles Papon · Apr 13, 2019, 8:41 AM UTC

5d1ec604b252

Added lrsc/amo tests

Charles Papon · Apr 9, 2019, 5:27 PM UTC

a6dc53044140

Add hardware AMO, require AMO=yes in sim and withAmo=true in linux.scala

Charles Papon · Apr 8, 2019, 11:22 PM UTC

fd42e7701e12

#60 Got instruction cache running linux :D

Charles Papon · Apr 1, 2019, 9:59 AM UTC

bc0af02c9742

Added a neutral LINUX_SOC for sim purposes

Dolu1990 · Mar 27, 2019, 9:53 AM UTC

f113946e6675

Fix some models missmatch Add more SBI Add hardware LR/SC support in dbus cacheless

Dolu1990 · Mar 26, 2019, 12:25 AM UTC

94fc2c3ecf51

Machine mode emulator

Dolu1990 · Mar 25, 2019, 1:00 AM UTC

9d55283b3ba2

#60 Add LitexSoC workspace / linux loading. Need to emulate peripherals and adapte the kernel now. Probably also need some machine mode emulation Software time !

Dolu1990 · Mar 24, 2019, 9:52 AM UTC

6c0608f0dd69

Add mdeleg tests

Dolu1990 · Mar 23, 2019, 10:41 AM UTC

3652ede1302d