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VexRiscv

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debugPlugin

AHBd2b324e32

BrieyAxi643bd940e89

Supervisor905abd5aa

compiler_plugind241f3562

dBusCachedRelaxMmuTranslation91f6bf513

debug-debug692f604dd

debugPlugin · selected0a0998fce

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pipelinedInterrupt357681a5c

reworkInstructionCache8ac4d7262

rework_fetch44005ebf3

rework_jump_flush7c3c4e8c8

riscv-debugbbbfc7ee6

rpls-mul16bb9261773

short-pipeline-fixes8d8c30166

simebda7526b

smpc12f9a378

spinal_1.1.70476de806

spinal_1.4.4551e76d24

spinalhdl_reworkDev838c13d68

thingatlas/import4b92aec63

tigthlyCoupled5df56bea7

tmpb40dc06b2

travis_debug7afe6cbef

watchpoint2cd19c89b

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Repository files

assets
doc
project
scripts
src
- main
- test
  - cpp
    briey
    common
    custom
    fpu
    murax
    raw
    amo
    common
    dcache
    deleg
    fpu
    icache
    lrsc
    machineCsr
    build
    src
    .gitignore
    makefile
    mmu
    pmp
    smp
    regression
  - java
  - python
  - resources
  - scala
.gitignore
.gitmodules
.travis.yml
build.sbt
LICENSE
README.md

Design files

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Repository / src / test / cpp / raw / machineCsr / makefile

Commit history

Dolu1990#176 fix typo0a0998fce

makefile139 bytes · GitDownload file

This file is pinned to the selected release. Download the original to open it in your design tool.

Repository / src / test / cpp / raw / machineCsr / makefile

Commit history

makefile139 bytes · GitDownload file

This file is pinned to the selected release. Download the original to open it in your design tool.

Source

ifeq ($(COMPRESSED),yes)
	PROJ_NAME=machineCsrCompressed
	CFLAGS=-DCOMPRESSED
else
	PROJ_NAME=machineCsr
endif




include ../common/asm.mk

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