VexRiscv

[*]
[*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI
[*] Tue Mar 14 21:27:40 2017
[*]
[dumpfile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/testA/rv32ui-p-lw.vcd"
[dumpfile_mtime] "Tue Mar 14 21:24:45 2017"
[dumpfile_size] 1017741
[savefile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/testA/yolo.gtkw"
[timestart] 41
[size] 1776 953
[pos] -1 -1
*-1.801840 49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] TOP.
[sst_width] 418
[signals_width] 559
[sst_expanded] 1
[sst_vpaned_height] 279
@28
TOP.clk
TOP.dCmd_valid
TOP.dCmd_ready
TOP.dCmd_payload_wr
@22
TOP.dCmd_payload_address[31:0]
TOP.dCmd_payload_data[31:0]
@28
TOP.dCmd_payload_size[1:0]
@23
TOP.dRsp_data[31:0]
@22
TOP.iCmd_payload_pc[31:0]
@28
TOP.iCmd_ready
TOP.iCmd_valid
@22
TOP.iRsp_inst[31:0]
@28
TOP.reset
TOP.clk
TOP.iCmd_valid
@22
TOP.iCmd_payload_pc[31:0]
@28
TOP.iCmd_ready
@22
TOP.iRsp_inst[31:0]
@28
TOP.reset
TOP.VexRiscv.writeBack_arbitration_isValid
@22
TOP.VexRiscv.writeBack_input_INSTRUCTION[31:0]
TOP.VexRiscv.writeBack_input_PC[31:0]
@28
TOP.VexRiscv.writeBack_RegFilePlugin_regFileWrite_valid
@22
TOP.VexRiscv.writeBack_RegFilePlugin_regFileWrite_payload_address[4:0]
TOP.VexRiscv.writeBack_RegFilePlugin_regFileWrite_payload_data[31:0]
@28
TOP.VexRiscv.prefetch_arbitration_isValid
TOP.VexRiscv.fetch_arbitration_isValid
TOP.VexRiscv.decode_arbitration_isValid
TOP.VexRiscv.execute_arbitration_isValid
TOP.VexRiscv.memory_arbitration_isValid
TOP.VexRiscv.writeBack_arbitration_isValid
TOP.VexRiscv.prefetch_arbitration_isStuck
TOP.VexRiscv.fetch_arbitration_isStuck
TOP.VexRiscv.decode_arbitration_isStuck
TOP.VexRiscv.execute_arbitration_isStuck
TOP.VexRiscv.memory_arbitration_isStuck
TOP.VexRiscv.writeBack_arbitration_isStuck
@22
TOP.VexRiscv.prefetch_input_PC[31:0]
TOP.VexRiscv.fetch_input_PC[31:0]
TOP.VexRiscv.decode_input_PC[31:0]
TOP.VexRiscv.execute_input_PC[31:0]
TOP.VexRiscv.memory_input_PC[31:0]
TOP.VexRiscv.writeBack_input_PC[31:0]
TOP.VexRiscv.fetch_input_INSTRUCTION[31:0]
TOP.VexRiscv.decode_input_INSTRUCTION[31:0]
TOP.VexRiscv.execute_input_INSTRUCTION[31:0]
TOP.VexRiscv.memory_input_INSTRUCTION[31:0]
TOP.VexRiscv.writeBack_input_INSTRUCTION[31:0]
[pattern_trace] 1
[pattern_trace] 0