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`default_nettype none
module servix
(
input wire i_clk,
output wire q);
parameter frequency = 32;
parameter memfile = "zephyr_hello.hex";
parameter memsize = 8192;
parameter PLL = "NONE";
wire wb_clk;
wire wb_rst;
servix_clock_gen
#(.frequency (frequency))
clock_gen
(.i_clk (i_clk),
.o_clk (wb_clk),
.o_rst (wb_rst));
servant
#(.memfile (memfile),
.memsize (memsize))
servant
(.wb_clk (wb_clk),
.wb_rst (wb_rst),
.q (q));
endmodule
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