Commits included in published releases. Unpublished intermediate commits are private. Showing matches from the latest 100 commits ending at this release.
PPU: Fix size-1 spans not being rendered, and add a testcase that covers this
Luke Wren · Dec 1, 2025, 10:52 PM UTC
25f8bb6eaebe
Update PPU tests for new CXXRTL
Luke Wren · Dec 1, 2025, 10:06 PM UTC
d48e3dc53bd2
Simplify comb logic on span_x0 and span_count outputs from PPU command processor
Luke Wren · Jul 4, 2023, 8:10 PM UTC
426a05dc8b3f
Simplify span_start logic by precomputing whether clip region is nonempty. (PPU frequency optimisation)
Luke Wren · Jul 3, 2023, 11:34 PM UTC
723c9fea71ca
Bump hazard5: move store data bypass to end of stage 3, to fix tight HWDATA path
Luke Wren · Jul 1, 2023, 6:01 PM UTC
3fa9f0cf0e57
Bump hazard5 for freq improvements (early decode of stage 3 bypass controls)
Luke Wren · Jul 1, 2023, 3:19 PM UTC
6d04950e2d55
Enable abc9 flow3 script for better synthesis results
Luke Wren · Jul 1, 2023, 12:42 PM UTC
9ce998e0017c
Change system frequency to 48 MHz -- note this currently does not meet timing, it's slightly aspirational
Luke Wren · Jun 26, 2023, 5:54 AM UTC
75245e318596
Resize PPU buffers for correct SRAM latency
Luke Wren · Jun 26, 2023, 5:51 AM UTC
ad44190ed8b7
Cut address bus from 21 to 20 bits
Luke Wren · Jun 26, 2023, 5:50 AM UTC
e44eac29b157
Disable bus errors in AHB splitter
Luke Wren · Jun 26, 2023, 5:48 AM UTC
ecde37add379
Bump hazard5 for frequency optimisations
Luke Wren · Jun 26, 2023, 5:44 AM UTC
fbc23c4dd32e
Tidy up early decompression for non-RVC hazard5
Luke Wren · Jun 25, 2023, 2:40 PM UTC
20b415f05457
sync SRAM: push write mask decode over into the next clock cycle
Luke Wren · Jun 24, 2023, 6:44 PM UTC
f8cc8eb8e6e1
Bump hazard5 for minor improvement to muldiv_seq stall output timing
Luke Wren · Jun 24, 2023, 4:44 PM UTC
ee2e69769581
Update APB bridge for improved HREADY output timing
Luke Wren · Jun 24, 2023, 4:42 PM UTC
2057b5534098
Simplify hready_resp logic in async SRAM controller
Luke Wren · Jun 24, 2023, 4:40 PM UTC
21157c3729d9
Bump processor: move instruction decompress from start of stage 2 to end of stage 1
Luke Wren · Jun 24, 2023, 12:25 PM UTC
d90fad80c7fc
Simplify handling of SRAM address LSB toggling
Luke Wren · Jun 24, 2023, 11:28 AM UTC
a93e3799359d
Simplify byte strobe logic in SRAM controller
Luke Wren · Jun 24, 2023, 1:58 AM UTC
0fdfb334f3ff
Fix up demo apps so they all build again
Luke Wren · Jun 23, 2023, 9:05 PM UTC
15f1084991a1
Fix bug in half-sized affine sprites introduced by previous PPU optimisations
Luke Wren · Jun 23, 2023, 8:51 PM UTC
0fdf45c6faf8
Fix tie-off value on tbio interface
Luke Wren · Jun 23, 2023, 8:35 PM UTC
0d2d517809ca
system tb: flush vcd buffer less frequently, for slightly faster sims with waves enabled
Luke Wren · Jun 23, 2023, 7:35 PM UTC
4b9e31824f38
Fucking Zicsr
Luke Wren · Jun 23, 2023, 6:27 PM UTC
762f63014a67
Revert accidental tagging of Hazard5 negedge reg read patch, which is not ready for prime time
Luke Wren · Jun 23, 2023, 6:26 PM UTC
7ede75ba9889
Fix numerous bugs in SRAM controller
Luke Wren · Jun 23, 2023, 3:21 PM UTC
1b980f5b7874
Add CXXRTL testcase for new SRAM controller, seems to have found a failure mode, will debug tomorrow
Luke Wren · Jun 22, 2023, 11:23 PM UTC
d7498f7a9a88
Small PPU frequency optimisations
Luke Wren · Jun 21, 2023, 10:06 PM UTC
8dbfa1878b38
Update some code for new tb_cxxrtl_io.h header
Luke Wren · Jun 21, 2023, 8:48 PM UTC
fef12ef96a96
WIP: new SRAM controller. Can run some code from SRAM, but once the PPU is running it eventually falls over
Luke Wren · Jun 21, 2023, 8:47 PM UTC
e3c0c8f94759
Add system-level CXXRTL simulator
Luke Wren · Jun 20, 2023, 10:05 PM UTC
816f0de831cf
Disable load/store alignment check as it costs quite a bit of fmax
Luke Wren · Jun 19, 2023, 4:38 PM UTC
9cf99b03fabf
Simplify the capture of instruction bits in S_EXECUTE
Luke Wren · Jun 16, 2023, 7:00 PM UTC
aa10ac568a12
Use simplified FILL-only coordinate comparisons for spans started from S_EXECUTE in cproc, to improve some long PPU reg2reg paths
Luke Wren · Jun 16, 2023, 6:46 PM UTC
9a9c4047aea7
Use 1R1W memory in SRAM1 to simplify write control path
Luke Wren · Jun 16, 2023, 6:46 PM UTC
c28544ea8742
PPU: cut path from bus aph ready -> coord gen adders, use a clock enable after the adders instead.
Luke Wren · Jun 16, 2023, 2:15 PM UTC
0181e7c20bde
Improve PPU bus timing by adding a separate valid bit to the address pipestage
Luke Wren · Jun 16, 2023, 1:56 PM UTC
87ec9780b3ea
Reduce most-significant decoded address bit, for area + freq improvement
Luke Wren · Jun 15, 2023, 2:42 PM UTC
335854b6329c
Bump hazard5 to set no_rw_check attribute on regfile memory. Remove -retime option from HX8K-EVN makefile.
Luke Wren · Jun 16, 2023, 12:26 PM UTC
24eaace06dbd
Oops, revert SRAM pipe stage accidentally enabled in SRAM PHY -- not ready for that yet
Luke Wren · Jun 16, 2023, 11:37 AM UTC
1da8fc3dff32
Add optional input pipestage to PPU bus interface. Write an AHB adapter for new PPU bus, and drop it into the existing system.
Luke Wren · Jun 16, 2023, 11:22 AM UTC
0e5fa711ab54
Make PPU bus interface safe at higher memory latencies by limiting the number of in-flight transfers
Luke Wren · Jun 16, 2023, 10:31 AM UTC
1d9b28815e63
Delete test artefact that shouldn't have been checked in
Luke Wren · Jun 16, 2023, 10:24 AM UTC
852b1270f818
Rewrite PPU bus interface for 16-bit pipestageable bus
Luke Wren · Jun 15, 2023, 7:27 PM UTC
d228e19bafd2
Register all output paths in SRAM PHY
Luke Wren · Jun 15, 2023, 2:11 PM UTC
a491b2278489
Fix up tb for new SRAM connection, I still have the old cursed sim setup on my thinkpad
Luke Wren · Jun 14, 2023, 8:32 PM UTC
796bc241b642
Fix byte enables missing connection in FPGA wrapper
Luke Wren · Jun 14, 2023, 8:30 PM UTC
75e63e9b1015
Start separating IOs from memory controller core, almost there but still something wrong with the byte strobes
Luke Wren · Jun 14, 2023, 5:09 PM UTC
289c8b35a0bb
Remove the following platforms:
Luke Wren · Jun 14, 2023, 2:43 PM UTC
1e16bba51fd0
Update .gitignore
Luke Wren · Jun 14, 2023, 7:12 PM UTC
008b19d4e564
Commit changes to mcu_lcd_test, assuming these were important
Luke Wren · Jun 14, 2023, 7:12 PM UTC
a05c0576b244
Avoid redefining CLK_SYS_MHZ in blinky
Luke Wren · Jun 14, 2023, 7:08 PM UTC
fd0c6d5e39a8
Commit whatever state the APU documentation section was in
Luke Wren · Oct 9, 2021, 10:40 AM UTC
df8713660878
Bump scripts: don't attempt to use broken SA placer in iCE40 seed sweeping
Luke Wren · Jun 14, 2023, 2:34 PM UTC
f56af4715afb
Update libfpga to remove unused clock enable from ddr_out
Luke Wren · Jun 14, 2023, 2:32 PM UTC
b0bc91c33617
Remove historic ppu1 implementation. Rename ppu2 to ppu.
Luke Wren · Jun 14, 2023, 2:01 PM UTC
6fe5708a650f
Workaround for AHB arbiter issue which was exposed by update to APB bridge
Luke Wren · Jun 12, 2023, 7:34 PM UTC
77de506a8d39
Fix synth regression: update scripts to use analytic placer on iCE40, and rename hazard5_cpu to hazard5_cpu_1port in riscboy_core.v