Commits included in published releases. Unpublished intermediate commits are private. Showing matches from the latest 100 commits ending at this release.
Merge branch 'master' into threecycle_return
Luke Wren · Feb 21, 2019, 11:35 PM UTC
ca74b33c62b4
Update readme: add links to open-source tools
Luke Wren · Feb 21, 2019, 11:30 PM UTC
daea63cd65eb
Add mandelbrot test (not run by default because it's VERY slow in simulation). Update readme.
Luke Wren · Feb 21, 2019, 11:24 PM UTC
8cba88d38c56
Add traffic generator to execution testbench to stress the stall logic a little.
Luke Wren · Feb 20, 2019, 7:57 PM UTC
353066a6473d
Reinstate system-level tests, apart from printf (needs more memory to run) and GPIO (gpio is hacked right now)
Luke Wren · Feb 20, 2019, 6:54 PM UTC
f22132473368
3-cycle branch passes compliance tests but fails system tests. Saves around 100 cells (many of them flops tho), but seems significantly slower, with long path through ALU to jump hardware.
Luke Wren · Feb 20, 2019, 5:04 PM UTC
cbfe36ccf1eb
Lay groundwork for 3-cycle return: remove special-purpose jump target adder in X. Calculate JALR target with ALU, and branch-NT-mispredict uses the value already calculated in D in case the branch was predicted taken. Was hoping for modest LUT savings but the extra muxing to deal with the two result paths (can't pass JAL linkaddr through ALU any more) has made it cost-neutral.
Luke Wren · Feb 20, 2019, 5:17 AM UTC
c6d19ca28ded
tbman: print cycle count after processor exits simulation
Luke Wren · Feb 20, 2019, 4:02 AM UTC
983b68584077
3 bugs related to CIR locking: - PC was updated to jump targe immediately, then incremented when locked instruction executes, so misaligned with jump target! fixed by gating PC update - Link address gets recalculated based on *target* PC whilst CIR is locked. Fixed by setting link address immediately on locking and then holding it in place - when exiting lock, frontend sees positive CIR usage and zero buffer level. These are subtracted to see if refill is needed, and subtraction underflows, to a value above the refill threshold. Fix is to do saturating subtract.
Luke Wren · Feb 19, 2019, 8:19 PM UTC
3524ddffd856
Clean up decode to enable removing reset from some flops. Made another 96 flops non-resettable (all of them masked by resettable pipeline controls).
Luke Wren · Feb 19, 2019, 4:51 PM UTC
4e2d3d9fc457
Disable jump requests whilst CIR contains a locked-in instruction. All compliance passes, and UART test passes for first time
Luke Wren · Feb 19, 2019, 4:48 AM UTC
68f1d64ac76e
First pass at CIR-locking functionality to preserve jump/predicted branch side effects if D jump is asserted whilst D is stalled. Tests pass if I disable it :)
Luke Wren · Feb 19, 2019, 4:12 AM UTC
0280cf2ef4da
Improve error message in listfiles
Luke Wren · Feb 19, 2019, 1:43 AM UTC
435c43b44df0
Correct preload hex filename in synth makefile
Luke Wren · Feb 19, 2019, 12:32 AM UTC
754b119a4aa3
Remove reset from datapath registers in pipeline. Reset fanout reduced by 176 (previously == 636 for full design)
Luke Wren · Feb 19, 2019, 12:31 AM UTC
321180b5c9bb
Fix execution tests broken by changes to SRAM preload. Modify SRAM preloading to zero out memory before preload when SIM is defined.
Luke Wren · Feb 18, 2019, 4:24 AM UTC
fe45274d716a
Fix some synthesis warnings in ahbl_arbiter and hazard5_decode (seemingly benign)
Luke Wren · Feb 1, 2019, 8:28 AM UTC
1a9214dcbcdd
Add minimal FPGA tb
Luke Wren · Feb 1, 2019, 4:37 AM UTC
21666c292571
Add module to dump an AHB-lite memory range as a raw BPMC serial, to assist with FPGA debugging
Luke Wren · Jan 31, 2019, 12:49 PM UTC
7130bfcb9b73
Use Clifford's suggested idiom for optional readmemh. Register GPIO inputs. Temporarily force UART onto corresponding GPIO.
Luke Wren · Jan 31, 2019, 12:45 PM UTC
55aa9a5bed0d
Fix staging in ice40 makefile. Fix simulation complaints in blinky
Luke Wren · Jan 31, 2019, 12:42 PM UTC
ceb7cbec32cd
Remove extra reset from PC which caused multiple driver issue, ultimately causing PC to be tied to 0. WHOOPS
Luke Wren · Jan 31, 2019, 10:30 AM UTC
23cc37d1d564
Build bootcode before synthesising FPGA.
Luke Wren · Jan 20, 2019, 7:09 PM UTC
5bca73752339
Small synth makefile changes
Luke Wren · Jan 20, 2019, 6:50 PM UTC
184ec74d0311
Add blinky .c file, and wire LED + UART correctly in FPGA top-level
Luke Wren · Jan 20, 2019, 6:33 PM UTC
3f69c0d82ff9
Use readmemh to directly preload the boot SRAM, as this is synthesisable (and the testbench hack wasn't). Update system TB to reflect this.
Luke Wren · Jan 20, 2019, 6:04 PM UTC
a19c2358aa28
Add simple address translation to vhexwidth. Move software to separate directory.
Luke Wren · Jan 20, 2019, 5:59 PM UTC
353861aabbc3
Add tool for converting different width verilog hex files
Luke Wren · Jan 20, 2019, 5:05 PM UTC
691825479a4a
First pass at working async sram controller (bus width matches sram width)
Luke Wren · Jan 20, 2019, 12:49 PM UTC
2a6f4a92babe
Sync up some scribblings from TODO file
Luke Wren · Jan 20, 2019, 10:46 AM UTC
66896b1d8b23
Working version of pi iceprog
Luke Wren · Jan 20, 2019, 12:15 AM UTC
82d3fdb15a0e
Initial checkin of raspberry pi FPGA configuration script
Luke Wren · Jan 19, 2019, 10:56 PM UTC
2779af8f3298
Board: correct mirrored oscillator footprint :(
Luke Wren · Jan 19, 2019, 10:06 PM UTC
385f185ca373
Add fix notes
Luke Wren · Dec 20, 2018, 11:17 PM UTC
5863d996fcd7
Add bom spreadsheet after ordering parts
Luke Wren · Dec 20, 2018, 10:23 PM UTC
e32c08acc1a7
Commit doodlings to sync from desktop to laptop
Luke Wren · Dec 2, 2018, 7:55 AM UTC
790cee4a9704
Generate gerbers for PCB and send it out for manufacture
Luke Wren · Nov 30, 2018, 8:03 PM UTC
600985503ebf
Update synth script for iCE40 to use NextPNR instead of Arachne
Luke Wren · Nov 30, 2018, 7:38 AM UTC
c9dab4139d1b
Add async SRAM model (untested)
Luke Wren · Nov 30, 2018, 1:46 AM UTC
ddd4532744d2
ALU optimisations. Shared adder for add/sub, saner comparisons. Saves around 100 LUTs from ALU (previous size ~570). Also provide direct adder output for load/store so that ALU muxing is not on the AHB setup path.
Luke Wren · Nov 30, 2018, 1:12 AM UTC
01916d8e567f
Decode: zero out specifier for unused register to avoid spurious load-use stalls.
Luke Wren · Nov 28, 2018, 8:58 PM UTC
83b8a6dad12f
Simplify operand muxing. Very small gate savings, hopefully a little more once linkaddr operand is eliminated.
Luke Wren · Nov 28, 2018, 8:44 PM UTC
6eb9c84c5d43
Separate storedata and M jump datapath; this is false economy on FPGA. Simplify jump decoding for modest gate savings.
Luke Wren · Nov 28, 2018, 10:21 AM UTC
8024ecf32fb6
Add some synth-time tieoffs to frontend to disable 16-bit support when C extension not present.
Luke Wren · Nov 28, 2018, 8:51 AM UTC
ae35206e3b0c
Factor instruction decode out into a separate file for synth experiments.
Luke Wren · Nov 28, 2018, 2:10 AM UTC
71dfb0d1da63
Add workaround for Yosys tristate inference issue (wrapper to instantiate SB_IO cell directly)
Luke Wren · Nov 28, 2018, 1:35 AM UTC
d0b2b29e3787
Add rudimentary FPGA top level using new constraints file. Build currently fails due to apparent yosys/arachne bug wrt tristate buffers.
Luke Wren · Nov 27, 2018, 7:40 PM UTC
e74d8da610cb
Update board render + schematic PDF
Luke Wren · Nov 27, 2018, 7:37 PM UTC
31ff3d7dace7
Correct orientation of LCD connector (oops), and add rudimentary audio to board.
Luke Wren · Nov 27, 2018, 7:24 PM UTC
1031126ee146
Add script to generate FPGA PCF from kicad netlist. Also some tidying up of the power supply routing.
Luke Wren · Nov 27, 2018, 12:29 AM UTC
0ef52d958b30
Tidy up potential ground antenna on backside plane (stitch + shorten)
Luke Wren · Nov 26, 2018, 8:35 PM UTC
3d8dbad93e90
Tidy up silk screen. Add some more ground stitching. Dress some traces. Add thermal thru-plane underneath SMPS
Luke Wren · Nov 26, 2018, 8:14 PM UTC
23e75dc37812
Add note about riscv-compliance submodule to readme
Luke Wren · Nov 26, 2018, 7:22 PM UTC
4de56ab72510
Rename to riscboy, avoid confusion with FPGA gameboy emulation projects
Luke Wren · Nov 26, 2018, 6:33 PM UTC
3b7abdc6729f
Silkscreen mk 2: electric boogaloo. Put first board render into readme.
Luke Wren · Nov 26, 2018, 1:19 AM UTC
c79d2ec3d5e3
First attempt to clean up the silkscreen. Fighting a losing battle...
Luke Wren · Nov 26, 2018, 12:59 AM UTC
0a2efcf05984
Update PDF following pinswapping for PCB
Luke Wren · Nov 26, 2018, 12:38 AM UTC
5b68c1935875
First clean DRC on the board.
Luke Wren · Nov 26, 2018, 12:36 AM UTC
d963cf678a5d
Connect up debug interface
Luke Wren · Nov 26, 2018, 12:02 AM UTC
27ae6575b4d3
Tidy up SD card routing. Fix some power routing.
Luke Wren · Nov 25, 2018, 11:16 PM UTC
3e78d024a9a4
More routing. No more ratsnests under the FPGA.
Luke Wren · Nov 25, 2018, 10:42 PM UTC
2a7f1d0becaa
More power layer routing: 5V, VBAT
Luke Wren · Nov 25, 2018, 9:46 PM UTC
cb7e7b422d68
More routing
Luke Wren · Nov 25, 2018, 8:18 PM UTC
60ab9944c53d
Route 1V2 net under FPGA
Luke Wren · Nov 25, 2018, 7:50 PM UTC
fc1dd7fe7560
Connect LCD interface
Luke Wren · Nov 25, 2018, 7:25 PM UTC
86824534bd45
Finish SRAM wiring.
Luke Wren · Nov 25, 2018, 7:01 PM UTC
035a3a488e38
Recovered pinswapping from undamaged schematic + netlist. Committing defensively.
Luke Wren · Nov 25, 2018, 6:51 PM UTC
0f002b1b797f
Kicad is a real piece of crap now. Froze while dragging trace and overwrote save, yet again (this was reason for previous commit). Luckily there was an autosave backup this time, which has 80% of what should have been in previous commit.
Luke Wren · Nov 25, 2018, 6:36 PM UTC
4ba1a5641f73
FPGA -> SRAM connected, still needs some tidying
Luke Wren · Nov 25, 2018, 6:31 PM UTC
d5087a28ee30
Pin-swapping + routing the SRAM: 50%
Luke Wren · Nov 25, 2018, 5:36 PM UTC
81e5e04d5702
BGA route out 99%. Use a gbin for an SRAM pin to avoid nasty route-out.
Luke Wren · Nov 25, 2018, 4:45 PM UTC
909dd2489a29
.
Luke Wren · Nov 25, 2018, 3:39 PM UTC
11d4a55627cb
Continue BGA escape. Pin-swap LCD and uSD card so that the traces don't have to cross.
Luke Wren · Nov 25, 2018, 2:56 PM UTC
e288dfd6e3eb
Start escaping from BGA
Luke Wren · Nov 25, 2018, 2:18 PM UTC
d9e46a724f5f
Add extra zones under BGA to tighten up plane clearance (so that planes can go between diagonally-spaced vias).
Luke Wren · Nov 25, 2018, 2:09 PM UTC
a1984f14b948
kicad crashed and deleted all traces from the board. wtf? 3 hours' progress lost. Only some vias under the BGA are left. Should commit more often
Luke Wren · Nov 25, 2018, 4:12 AM UTC
e295c73355d4
First pass of placing all components.
Luke Wren · Nov 24, 2018, 11:38 PM UTC
eb91bc9deabc
Correct formatting in readme
Luke Wren · Nov 24, 2018, 10:15 PM UTC
1e5e6a55e7c5
Update some diagrams in documentation
Luke Wren · Nov 24, 2018, 10:13 PM UTC
566457ef61a9
Part placement for switchmode supply. Remove silkscreen on pad in BGA footprint.
Luke Wren · Nov 24, 2018, 8:13 PM UTC
84fc75998a96
Start placing components. Fix references to kicad4 footprints. Alter BGA footprint so that vias can be placed between pads.
Luke Wren · Nov 24, 2018, 7:12 PM UTC
f17a7b1e42f5
PCB: import netlist, set up board perimeter, planes, DRC.
Luke Wren · Nov 24, 2018, 6:41 PM UTC
0ba6485da09e
Fix ERCs on schematic (SRAM controls unconnected oops). Ready for layout!
Luke Wren · Nov 24, 2018, 6:03 PM UTC
74a130e8a638
More minor schematic revisions. Update readme to be in line with recent makefile changes.
Luke Wren · Nov 24, 2018, 5:23 PM UTC
eacbfb2340f6
Fix some issues following schematic review: correct connection of GNDPLL. Additional pullups on FPGA cfg interface. Correct symbol for SD card, which has correct pin numbering. Pullups on UART.
Luke Wren · Nov 24, 2018, 4:00 PM UTC
b7c6e6e27847
Add resistor network package. All parts have packages now.
Luke Wren · Nov 24, 2018, 2:35 PM UTC
4f12491704ee
Add switch debouncer module
Luke Wren · Nov 24, 2018, 2:34 PM UTC
ceee8ed9ddef
Add QFN + BGA footprints for micro + FPGA
Luke Wren · Nov 24, 2018, 4:31 AM UTC
ac34dce8d878
Wire out the microcontroller for configuring the FPGA (schematic). Tidy up the schematic and plot a new PDF.
Luke Wren · Nov 24, 2018, 4:14 AM UTC
c7d5f5e0eabd
Create symbol for SAML22G18A, and wire up its reset + power in schematic.
Luke Wren · Nov 24, 2018, 2:39 AM UTC
99fa1518e70d
Add CPU synth results to bottom of TODO. Delete old checkout of previous processor version (shouldn't have been commited)
Luke Wren · Nov 23, 2018, 1:29 AM UTC
0e75d49f70ca
Update TODO after ATXMEGA boot investigation. Small schematic updates. Specify a power inductor for buck converters.
Luke Wren · Nov 23, 2018, 1:01 AM UTC
df5b49f22b95
Schematic: remove FT2232H. Add debug connector. Add datasheet for a better microcontroller.
Luke Wren · Nov 23, 2018, 12:00 AM UTC
719440b8dee2
Datasheets: remove old SPI flash, add uSD socket. Also update todo.
Luke Wren · Nov 22, 2018, 9:51 PM UTC
26c7fa8cd5a1
Add todo file (using PlainTasks in sublime)
Luke Wren · Nov 22, 2018, 9:24 PM UTC
28f929ece244
Add UART TX test. Fix bug in uart_mini where FIFO would be popped while clk_en low.
Luke Wren · Nov 21, 2018, 11:03 PM UTC
043289ffa6f7
Add behavioural UART receiver to system tb
Luke Wren · Nov 21, 2018, 1:43 AM UTC
3b1f9ce429ac
Correct GPIO muxing logic. Add behavioural unaligned access exception to processor. Add GPIO testcase, and a couple of other small tests (which didn't find any bugs).
Luke Wren · Nov 20, 2018, 3:48 AM UTC
2165e125bddf
Add int output to tbman (saves doing printf when you are dumping memory etc)