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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Mon Oct 26 07:25:13 2020
| Host : cluster1 running 64-bit unknown
| Command : report_power -file xilinx_u250_xdma_201830_2_bb_locked_power_routed.rpt -pb xilinx_u250_xdma_201830_2_bb_locked_power_summary_routed.pb -rpx xilinx_u250_xdma_201830_2_bb_locked_power_routed.rpx
| Design : pfm_top_wrapper
| Device : xcu250-figd2104-2L-e
| Design State : routed
| Grade : extended
| Process : typical
| Characterization : Production
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Power Report
Table of Contents
-----------------
1. Summary
1.1 On-Chip Components
1.2 Power Supply Summary
1.3 Confidence Level
2. Settings
2.1 Environment
2.2 Clock Constraints
3. Detailed Reports
3.1 By Hierarchy
1. Summary
----------
+--------------------------+--------------+
| Total On-Chip Power (W) | 24.765 |
| Design Power Budget (W) | Unspecified* |
| Power Budget Margin (W) | NA |
| Dynamic (W) | 21.245 |
| Device Static (W) | 3.521 |
| Effective TJA (C/W) | 0.5 |
| Max Ambient (C) | 87.1 |
| Junction Temperature (C) | 37.9 |
| Confidence Level | Low |
| Setting File | --- |
| Simulation Activity File | --- |
| Design Nets Matched | NA |
+--------------------------+--------------+
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
1.1 On-Chip Components
----------------------
+--------------------------+-----------+----------+-----------+-----------------+
| On-Chip | Power (W) | Used | Available | Utilization (%) |
+--------------------------+-----------+----------+-----------+-----------------+
| Clocks | 2.361 | 68 | --- | --- |
| CLB Logic | 5.255 | 742879 | --- | --- |
| LUT as Logic | 4.495 | 310915 | 1727040 | 18.00 |
| CARRY8 | 0.305 | 17108 | 215880 | 7.92 |
| LUT as Distributed RAM | 0.262 | 9933 | 790560 | 1.26 |
| Register | 0.112 | 298060 | 3454080 | 8.63 |
| LUT as Shift Register | 0.082 | 3732 | 790560 | 0.47 |
| Others | <0.001 | 8795 | --- | --- |
| BUFG | 0.000 | 1 | 128 | 0.78 |
| F7/F8 Muxes | 0.000 | 2809 | 1727040 | 0.16 |
| Signals | 5.403 | 593298 | --- | --- |
| Block RAM | 1.045 | 227.5 | 2688 | 8.46 |
| MMCM | 0.308 | 0 | --- | --- |
| PLL | 0.385 | 7 | --- | --- |
| DSPs | 0.917 | 609 | 12288 | 4.96 |
| I/O | 0.799 | 163 | 676 | 24.11 |
| GTY | 4.360 | 16 | 24 | 66.67 |
| SYSMON | 0.019 | 1 | --- | --- |
| Hard IPs | 0.391 | 1 | --- | --- |
| PCIE | 0.391 | 1 | --- | --- |
| Static Power | 3.521 | | | |
| Total | 24.765 | | | |
+--------------------------+-----------+----------+-----------+-----------------+
1.2 Power Supply Summary
------------------------
+------------+-------------+-----------+-------------+------------+
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
+------------+-------------+-----------+-------------+------------+
| Vccint | 0.850 | 20.456 | 18.660 | 1.796 |
| Vccint_io | 0.850 | 0.575 | 0.424 | 0.151 |
| Vccbram | 0.850 | 0.192 | 0.161 | 0.031 |
| Vccaux | 1.800 | 1.227 | 0.379 | 0.848 |
| Vccaux_io | 1.800 | 0.271 | 0.167 | 0.104 |
| Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 |
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 |
| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 |
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 |
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 |
| Vcco12 | 1.200 | 0.115 | 0.115 | 0.000 |
| Vcco10 | 1.000 | 0.000 | 0.000 | 0.000 |
| Vccadc | 1.800 | 0.032 | 0.000 | 0.032 |
| MGTYAVcc | 0.900 | 0.662 | 0.616 | 0.046 |
| MGTYAVtt | 1.200 | 2.554 | 2.536 | 0.018 |
| MGTYVccaux | 1.800 | 0.096 | 0.093 | 0.002 |
+------------+-------------+-----------+-------------+------------+
1.3 Confidence Level
--------------------
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| User Input Data | Confidence | Details | Action |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| Design implementation state | High | Design is routed | |
| Clock nodes activity | High | User specified more than 95% of clocks | |
| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
| Device models | High | Device models are Production | |
| | | | |
| Overall confidence level | Low | | |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
2. Settings
-----------
2.1 Environment
---------------
+-----------------------+--------------------------+
| Ambient Temp (C) | 25.0 |
| ThetaJA (C/W) | 0.5 |
| Airflow (LFM) | 250 |
| Heat Sink | medium (Medium Profile) |
| ThetaSA (C/W) | 0.7 |
| Board Selection | medium (10"x10") |
| # of Board Layers | 12to15 (12 to 15 Layers) |
| Board Temperature (C) | 25.0 |
+-----------------------+--------------------------+
2.2 Clock Constraints
---------------------
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+
| Clock | Domain | Constraint (ns) |
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+
| c0_sys_clk_p | c0_sys_clk_p | 3.3 |
| c1_sys_clk | c1_sys_clk_p[0] | 3.3 |
| c1_sys_clk | pfm_top_i/static_region/c1_sys_bugf/U0/BUFG_O[0] | 3.3 |
| c2_sys_clk_p | c2_sys_clk_p | 3.3 |
| c3_sys_clk_p | c3_sys_clk_p | 3.3 |
| clk_out1_pfm_top_clk_wiz_0_0 | pfm_top_i/static_region/slr0/base_clocking/clk_wiz_0/inst/clk_out1_pfm_top_clk_wiz_0_0 | 20.0 |
| clk_out1_pfm_top_clkwiz_kernel2_0_1 | pfm_top_i/static_region/slr0/base_clocking/clkwiz_kernel2/inst/CLK_CORE_DRP_I/clk_inst/clk_out1_pfm_top_clkwiz_kernel2_0 | 2.0 |
| clk_out1_pfm_top_clkwiz_kernel_0_1 | pfm_top_i/static_region/slr0/base_clocking/clkwiz_kernel/inst/CLK_CORE_DRP_I/clk_inst/clk_out1_pfm_top_clkwiz_kernel_0 | 3.3 |
| clk_out1_pfm_top_clkwiz_pcie_0_1 | pfm_top_i/static_region/slr0/base_clocking/clkwiz_pcie/inst/clk_out1_pfm_top_clkwiz_pcie_0 | 10.0 |
| clk_out1_pfm_top_clkwiz_scheduler_0_1 | pfm_top_i/static_region/slr0/base_clocking/clkwiz_scheduler/inst/clk_out1_pfm_top_clkwiz_scheduler_0 | 4.0 |
| clk_out2_pfm_top_clk_wiz_0_0 | pfm_top_i/static_region/slr0/base_clocking/clk_wiz_0/inst/clk_out2_pfm_top_clk_wiz_0_0 | 10.0 |
| clk_out2_pfm_top_clkwiz_sysclks_0_1 | pfm_top_i/static_region/slr0/base_clocking/clkwiz_sysclks/inst/clk_out2_pfm_top_clkwiz_sysclks_0 | 19.6 |
| diablo_gt.diablo_gt_phy_wrapper/pclk2_gt_1 | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/CLK_PCLK2_GT | 4.0 |
| mcap_clk_1 | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/CLK_MCAPCLK | 8.0 |
| microblaze_0_Clk_1 | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/CLK_USERCLK | 4.0 |
| mmcm_clkout0 | pfm_top_i/dynamic_region/memory_subsystem/inst/memory/ddr4_mem00/inst/u_ddr4_infrastructure/mmcm_clkout0 | 3.3 |
| mmcm_clkout6 | pfm_top_i/dynamic_region/memory_subsystem/inst/memory/ddr4_mem00/inst/u_ddr4_infrastructure/mmcm_clkout6 | 6.7 |
| pfm_top_i/static_region/slr1/jtag_fallback/inst/bs_switch/inst/BSCAN_SWITCH.N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK | pfm_top_i/static_region/slr1/jtag_fallback/inst/bs_switch/inst/BSCAN_SWITCH.N_EXT_BSCAN.bscan_inst/BSCAN_SWITCH.N_EXT_BSCAN.tck_bs | 33.0 |
| pfm_top_i/static_region/slr1/mdm_board_control/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O | pfm_top_i/static_region/slr1/mdm_board_control/U0/No_Dbg_Reg_Access.BUFG_DRCK/Ext_JTAG_DRCK | 157.1 |
| pfm_top_i/static_region/slr1/mdm_board_control/U0/Use_External.Use_BSCANID.No_Dbg_Reg_Access.BUFG_UPDATE/Using_FPGA.Native/O | pfm_top_i/static_region/slr1/mdm_board_control/U0/Use_External.Use_BSCANID.No_Dbg_Reg_Access.BUFG_UPDATE/Dbg_Update_0 | 66.0 |
| pfm_top_i/static_region/slr1/mgmt_debug_bridge/inst/axi_jtag/inst/u_jtag_proc/tck_i_reg/Q | pfm_top_i/static_region/slr1/mgmt_debug_bridge/inst/axi_jtag/inst/u_jtag_proc/tck | 157.1 |
| pfm_top_i/static_region/slr1/mgmt_debug_bridge/inst/bsip/inst/USE_SOFTBSCAN.U_BSCAN_TAP/U_BASETAP/U_TAP/UPDATEDR_O_reg/Q | pfm_top_i/static_region/slr1/mgmt_debug_bridge/inst/bsip/inst/USE_SOFTBSCAN.U_BSCAN_TAP/U_BASETAP/U_TAP/UPDATEDR_O | 157.1 |
| pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[28].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[28].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/txoutclk_out[0] | 2.0 |
| pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[28].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[28].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/txoutclk_out[1] | 2.0 |
| pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[28].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[28].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/txoutclk_out[2] | 2.0 |
| pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[28].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[28].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/txoutclk_out[3] | 2.0 |
| pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[28].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/txoutclk_out[0] | 2.0 |
| pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[28].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/txoutclk_out[1] | 2.0 |
| pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[28].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/txoutclk_out[2] | 2.0 |
| pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[28].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/txoutclk_out[3] | 2.0 |
| pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[28].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[30].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/txoutclk_out[0] | 2.0 |
| pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[28].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[30].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/txoutclk_out[1] | 2.0 |
| pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[28].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[30].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/txoutclk_out[2] | 2.0 |
| pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[28].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[30].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/txoutclk_out[3] | 2.0 |
| pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[28].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[31].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/txoutclk_out[0] | 2.0 |
| pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[28].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[31].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/txoutclk_out[1] | 2.0 |
| pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[28].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[31].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/txoutclk_out[2] | 2.0 |
| pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[28].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[31].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/txoutclk_out[3] | 2.0 |
| pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_tx_i/txoutclkmon | 8.0 |
| pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_tx_i/txoutclkmon | 8.0 |
| pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_tx_i/txoutclkmon | 8.0 |
| pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_tx_i/txoutclkmon | 8.0 |
| pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_tx_i/txoutclkmon | 8.0 |
| pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_tx_i/txoutclkmon | 8.0 |
| pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_tx_i/txoutclkmon | 8.0 |
| pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_tx_i/txoutclkmon | 8.0 |
| pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_tx_i/txoutclkmon | 8.0 |
| pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_tx_i/txoutclkmon | 8.0 |
| pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_tx_i/txoutclkmon | 8.0 |
| pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_tx_i/txoutclkmon | 8.0 |
| pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_tx_i/txoutclkmon | 8.0 |
| pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_tx_i/txoutclkmon | 8.0 |
| pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_tx_i/txoutclkmon | 8.0 |
| pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_5_gtye4_cpll_cal_tx_i/txoutclkmon | 8.0 |
| pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/CLK_INTCLK | 1000.0 |
| pfm_top_i/static_region/slr1/user_debug_bridge/inst/axi_jtag/inst/u_jtag_proc/tck_i_reg/Q | pfm_top_i/static_region/slr1/user_debug_bridge/inst/axi_jtag/inst/u_jtag_proc/tck | 157.1 |
| pfm_top_i/static_region/slr1/user_debug_bridge/inst/bsip/inst/USE_SOFTBSCAN.U_BSCAN_TAP/U_BASETAP/U_TAP/UPDATEDR_O_reg/Q | pfm_top_i/static_region/slr1/user_debug_bridge/inst/bsip/inst/USE_SOFTBSCAN.U_BSCAN_TAP/U_BASETAP/U_TAP/UPDATEDR_O | 157.1 |
| pll_clk[0] | pfm_top_i/dynamic_region/memory_subsystem/inst/memory/ddr4_mem00/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/pll_clk[0] | 0.4 |
| pll_clk[0]_DIV | pfm_top_i/dynamic_region/memory_subsystem/inst/memory/ddr4_mem00/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/TX_BIT_CTRL_OUT0[26] | 3.3 |
| pll_clk[1] | pfm_top_i/dynamic_region/memory_subsystem/inst/memory/ddr4_mem00/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/pll_clk[1] | 0.4 |
| pll_clk[1]_DIV | pfm_top_i/dynamic_region/memory_subsystem/inst/memory/ddr4_mem00/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/TX_BIT_CTRL_OUT0[26] | 3.3 |
| pll_clk[2] | pfm_top_i/dynamic_region/memory_subsystem/inst/memory/ddr4_mem00/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/pll_clk[2] | 0.4 |
| pll_clk[2]_DIV | pfm_top_i/dynamic_region/memory_subsystem/inst/memory/ddr4_mem00/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/TX_BIT_CTRL_OUT2[26] | 3.3 |
| qpll0outclk_out[0] | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_common.gen_common_container[28].gen_enabled_common.gtye4_common_wrapper_inst/common_inst/qpll0outclk_out[0] | 0.2 |
| qpll0outclk_out[0]_1 | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_common.gen_common_container[29].gen_enabled_common.gtye4_common_wrapper_inst/common_inst/qpll0outclk_out[0] | 0.2 |
| qpll0outclk_out[0]_2 | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_common.gen_common_container[30].gen_enabled_common.gtye4_common_wrapper_inst/common_inst/qpll0outclk_out[0] | 0.2 |
| qpll0outclk_out[0]_3 | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_common.gen_common_container[31].gen_enabled_common.gtye4_common_wrapper_inst/common_inst/qpll0outclk_out[0] | 0.2 |
| qpll0outrefclk_out[0] | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_common.gen_common_container[28].gen_enabled_common.gtye4_common_wrapper_inst/common_inst/qpll0outrefclk_out[0] | 10.0 |
| qpll0outrefclk_out[0]_1 | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_common.gen_common_container[29].gen_enabled_common.gtye4_common_wrapper_inst/common_inst/qpll0outrefclk_out[0] | 10.0 |
| qpll0outrefclk_out[0]_2 | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_common.gen_common_container[30].gen_enabled_common.gtye4_common_wrapper_inst/common_inst/qpll0outrefclk_out[0] | 10.0 |
| qpll0outrefclk_out[0]_3 | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_common.gen_common_container[31].gen_enabled_common.gtye4_common_wrapper_inst/common_inst/qpll0outrefclk_out[0] | 10.0 |
| qpll1outclk_out[0] | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_common.gen_common_container[28].gen_enabled_common.gtye4_common_wrapper_inst/common_inst/qpll1outclk_out[0] | 0.2 |
| qpll1outclk_out[0]_1 | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_common.gen_common_container[29].gen_enabled_common.gtye4_common_wrapper_inst/common_inst/qpll1outclk_out[0] | 0.2 |
| qpll1outclk_out[0]_2 | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_common.gen_common_container[30].gen_enabled_common.gtye4_common_wrapper_inst/common_inst/qpll1outclk_out[0] | 0.2 |
| qpll1outclk_out[0]_3 | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_common.gen_common_container[31].gen_enabled_common.gtye4_common_wrapper_inst/common_inst/qpll1outclk_out[0] | 0.2 |
| qpll1outrefclk_out[0] | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_common.gen_common_container[28].gen_enabled_common.gtye4_common_wrapper_inst/common_inst/qpll1outrefclk_out[0] | 10.0 |
| qpll1outrefclk_out[0]_1 | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_common.gen_common_container[29].gen_enabled_common.gtye4_common_wrapper_inst/common_inst/qpll1outrefclk_out[0] | 10.0 |
| qpll1outrefclk_out[0]_2 | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_common.gen_common_container[30].gen_enabled_common.gtye4_common_wrapper_inst/common_inst/qpll1outrefclk_out[0] | 10.0 |
| qpll1outrefclk_out[0]_3 | pfm_top_i/static_region/slr1/pcie/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pfm_top_pcie_0_gt_i/inst/gen_gtwizard_gtye4_top.pfm_top_pcie_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_common.gen_common_container[31].gen_enabled_common.gtye4_common_wrapper_inst/common_inst/qpll1outrefclk_out[0] | 10.0 |
| ref_clk | ref_clk_clk_p[0] | 10.0 |
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+
3. Detailed Reports
-------------------
3.1 By Hierarchy
----------------
+------------------------------------------+-----------+
| Name | Power (W) |
+------------------------------------------+-----------+
| pfm_top_wrapper | 21.244 |
| pfm_top_i | 21.241 |
| dynamic_region | 12.788 |
| debug_bridge_xsdbm | 0.002 |
| hastip_1 | 9.813 |
| memory_subsystem | 2.376 |
| slr0 | 0.321 |
| slr1 | 0.076 |
| slr2 | 0.081 |
| slr3 | 0.078 |
| static_region | 8.453 |
| axi_ctrl_tdm_regslice_slr1_to_slr0 | 0.019 |
| axi_mb_regslice_slr0_to_slr1 | 0.003 |
| axi_mgmt_tdm_regslice_slr1_to_slr0 | 0.011 |
| axi_mgmt_tdm_regslice_slr2_to_slr1 | 0.023 |
| axi_user_tdm_regslice_slr1_to_slr0 | 0.026 |
| axi_user_tdm_regslice_slr2_to_slr1 | 0.021 |
| axis_regslice_cc | 0.036 |
| axis_regslice_cq | 0.044 |
| axis_regslice_rc | 0.043 |
| axis_regslice_rq | 0.040 |
| c1_sys_ds_buf | 0.002 |
| ddr_tdm_regslice_slr1_to_slr0 | 0.170 |
| ddr_tdm_regslice_slr2_to_slr1 | 0.181 |
| ddr_tdm_regslice_slr2_to_slr3 | 0.108 |
| dma_aresetn_fanout | 0.001 |
| dma_pcie | 0.766 |
| slr0 | 0.826 |
| slr1 | 5.882 |
| slr2 | 0.225 |
| slr3 | 0.024 |
+------------------------------------------+-----------+