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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Sun Oct 25 03:39:12 2020
| Host : cluster1 running 64-bit Ubuntu 18.04.5 LTS
| Command : report_utilization -file /tmp/david.el-saig/u250/HardwareFramework/reports/36a0b0eaefd20bf74638ef99659296a7a9f6c354e4dec750d7ae19275f7ea087/Hast_IP_synth_util.rpt
| Design : Hast_IP
| Device : xcu250figd2104-2L
| Design State : Synthesized
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Utilization Design Information
Table of Contents
-----------------
1. CLB Logic
1.1 Summary of Registers by Type
2. BLOCKRAM
3. ARITHMETIC
4. I/O
5. CLOCK
6. ADVANCED
7. CONFIGURATION
8. Primitives
9. Black Boxes
10. Instantiated Netlists
11. SLR Connectivity
12. SLR Connectivity Matrix
13. SLR CLB Logic and Dedicated Block Utilization
14. SLR IO Utilization
1. CLB Logic
------------
+-------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------+-------+-------+-----------+-------+
| CLB LUTs* | 25034 | 0 | 1728000 | 1.45 |
| LUT as Logic | 25034 | 0 | 1728000 | 1.45 |
| LUT as Memory | 0 | 0 | 791040 | 0.00 |
| CLB Registers | 10098 | 0 | 3456000 | 0.29 |
| Register as Flip Flop | 10098 | 0 | 3456000 | 0.29 |
| Register as Latch | 0 | 0 | 3456000 | 0.00 |
| CARRY8 | 2258 | 0 | 216000 | 1.05 |
| F7 Muxes | 48 | 0 | 864000 | <0.01 |
| F8 Muxes | 0 | 0 | 432000 | 0.00 |
| F9 Muxes | 0 | 0 | 216000 | 0.00 |
+-------------------------+-------+-------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 10098 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. BLOCKRAM
-----------
+----------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| Block RAM Tile | 0 | 0 | 2688 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 2688 | 0.00 |
| RAMB18 | 0 | 0 | 5376 | 0.00 |
| URAM | 0 | 0 | 1280 | 0.00 |
+----------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E2 or one FIFO18E2. However, if a FIFO18E2 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E2
3. ARITHMETIC
-------------
+----------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| DSPs | 82 | 0 | 12288 | 0.67 |
| DSP48E2 only | 82 | | | |
+----------------+------+-------+-----------+-------+
4. I/O
------
+------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| Bonded IOB | 136 | 0 | 676 | 20.12 |
+------------+------+-------+-----------+-------+
5. CLOCK
--------
+----------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------+------+-------+-----------+-------+
| GLOBAL CLOCK BUFFERs | 1 | 0 | 1344 | 0.07 |
| BUFGCE | 1 | 0 | 384 | 0.26 |
| BUFGCE_DIV | 0 | 0 | 64 | 0.00 |
| BUFG_GT | 0 | 0 | 768 | 0.00 |
| BUFGCTRL* | 0 | 0 | 128 | 0.00 |
| PLL | 0 | 0 | 32 | 0.00 |
| MMCM | 0 | 0 | 16 | 0.00 |
+----------------------+------+-------+-----------+-------+
* Note: Each used BUFGCTRL counts as two GLOBAL CLOCK BUFFERs. This table does not include global clocking resources, only buffer cell usage. See the Clock Utilization Report (report_clock_utilization) for detailed accounting of global clocking resource availability.
6. ADVANCED
-----------
+-----------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------+------+-------+-----------+-------+
| CMACE4 | 0 | 0 | 12 | 0.00 |
| GTYE4_CHANNEL | 0 | 0 | 24 | 0.00 |
| GTYE4_COMMON | 0 | 0 | 6 | 0.00 |
| ILKNE4 | 0 | 0 | 8 | 0.00 |
| OBUFDS_GTE4 | 0 | 0 | 12 | 0.00 |
| OBUFDS_GTE4_ADV | 0 | 0 | 12 | 0.00 |
| PCIE40E4 | 0 | 0 | 4 | 0.00 |
| SYSMONE4 | 0 | 0 | 4 | 0.00 |
+-----------------+------+-------+-----------+-------+
7. CONFIGURATION
----------------
+-------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2 | 0 | 0 | 16 | 0.00 |
| DNA_PORTE2 | 0 | 0 | 4 | 0.00 |
| EFUSE_USR | 0 | 0 | 4 | 0.00 |
| FRAME_ECCE4 | 0 | 0 | 4 | 0.00 |
| ICAPE3 | 0 | 0 | 8 | 0.00 |
| MASTER_JTAG | 0 | 0 | 4 | 0.00 |
| STARTUPE3 | 0 | 0 | 4 | 0.00 |
+-------------+------+-------+-----------+-------+
8. Primitives
-------------
+----------+-------+---------------------+
| Ref Name | Used | Functional Category |
+----------+-------+---------------------+
| FDRE | 10098 | Register |
| LUT2 | 7557 | CLB |
| LUT6 | 6970 | CLB |
| LUT3 | 6911 | CLB |
| LUT5 | 4492 | CLB |
| LUT4 | 3428 | CLB |
| CARRY8 | 2258 | CLB |
| LUT1 | 1773 | CLB |
| DSP48E2 | 82 | Arithmetic |
| INBUF | 69 | I/O |
| IBUFCTRL | 69 | Others |
| OBUF | 67 | I/O |
| MUXF7 | 48 | CLB |
| BUFGCE | 1 | Clock |
+----------+-------+---------------------+
9. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
10. Instantiated Netlists
-------------------------
+----------+------+
| Ref Name | Used |
+----------+------+
11. SLR Connectivity
--------------------
+----------------------------------+------+-------+-----------+-------+
| | Used | Fixed | Available | Util% |
+----------------------------------+------+-------+-----------+-------+
| SLR3 <-> SLR2 | 0 | | 23040 | 0.00 |
| SLR2 -> SLR3 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR3 -> SLR2 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR2 <-> SLR1 | 0 | | 23040 | 0.00 |
| SLR1 -> SLR2 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR2 -> SLR1 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR1 <-> SLR0 | 0 | | 23040 | 0.00 |
| SLR0 -> SLR1 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR1 -> SLR0 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
+----------------------------------+------+-------+-----------+-------+
| Total SLLs Used | 0 | | | |
+----------------------------------+------+-------+-----------+-------+
12. SLR Connectivity Matrix
---------------------------
+-----------+------+------+------+------+
| FROM \ TO | SLR3 | SLR2 | SLR1 | SLR0 |
+-----------+------+------+------+------+
| SLR3 | 0 | 0 | 0 | 0 |
| SLR2 | 0 | 0 | 0 | 0 |
| SLR1 | 0 | 0 | 0 | 0 |
| SLR0 | 0 | 0 | 0 | 0 |
+-----------+------+------+------+------+
13. SLR CLB Logic and Dedicated Block Utilization
-------------------------------------------------
+----------------------------+------+------+------+------+--------+--------+--------+--------+
| Site Type | SLR0 | SLR1 | SLR2 | SLR3 | SLR0 % | SLR1 % | SLR2 % | SLR3 % |
+----------------------------+------+------+------+------+--------+--------+--------+--------+
| CLB | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
| CLBL | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
| CLBM | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
| CLB LUTs | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
| LUT as Logic | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
| LUT as Memory | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
| LUT as Distributed RAM | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
| LUT as Shift Register | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
| CLB Registers | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
| CARRY8 | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
| F7 Muxes | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
| F8 Muxes | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
| F9 Muxes | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
| Block RAM Tile | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
| RAMB36/FIFO | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
| RAMB18 | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
| URAM | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
| DSPs | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
| PLL | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
| MMCM | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
| Unique Control Sets | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
+----------------------------+------+------+------+------+--------+--------+--------+--------+
* Note: Available Control Sets based on CLB Registers / 8
14. SLR IO Utilization
----------------------
+-----------+-----------+---------+------------+----------+------------+----------+-----+
| SLR Index | Used IOBs | (%)IOBs | Used IPADs | (%)IPADs | Used OPADs | (%)OPADs | GTs |
+-----------+-----------+---------+------------+----------+------------+----------+-----+
| SLR3 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
| SLR2 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
| SLR1 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
| SLR0 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
+-----------+-----------+---------+------------+----------+------------+----------+-----+
| Total | 0 | | 0 | | 0 | | 0 |
+-----------+-----------+---------+------------+----------+------------+----------+-----+
7f9864208This file is pinned to the selected release. Download the original to open it in your design tool.