chiselv

CAPI=2:

name: carlosedp:chiselv:singlecycle:0
description: ChiselV is a RV32I core written in Chisel

filesets:
  # These are the demo filesets, use the `&demofiles` tag for the one to be used
  gpiodemo:
    files:
      - gcc/blinkLED/main-rom.mem: { copyto: progload.mem, file_type: user }
      - gcc/blinkLED/main-ram.mem: { copyto: progload-RAM.mem, file_type: user }

  uartdemo: &demofiles
    files:
      - gcc/helloUART/main-rom.mem: { copyto: progload.mem, file_type: user }
      - gcc/helloUART/main-ram.mem:
          { copyto: progload-RAM.mem, file_type: user }

  # This is the fileset to be programmed into the FPGA
  progload:
    <<: *demofiles

  # Show the programming info for the FPGAs
  proginfo:
    files:
      - proginfo/proginfo.py: { file_type: user, copyto: proginfo.py }
      - proginfo/boardconfig.yaml: { file_type: user, copyto: boardconfig.yaml }

  base:
    depend: ["fusesoc:utils:generators"]

  # Files specific to each FPGA board
  ulx3s-85:
    files:
      - constraints/ecp5-ulx3s.lpf: { file_type: LPF }
      - openocd/ft231x.cfg: { file_type: user }
      - openocd/LFE5U-85F.cfg: { file_type: user }
      - proginfo/ulx3s-template.txt: { file_type: user }

  artya7-35t:
    files:
      - constraints/arty_a7.xdc: { file_type: xdc }
      - openocd/digilent-hs1.cfg: { file_type: user }
      - openocd/xilinx-xc7.cfg: { file_type: user }
      - proginfo/artix7-template.txt: { file_type: user }

  qmtech_k325t:
    files:
      - constraints/qmtech-kintex7.xdc: { file_type: XDC }
      - proginfo/qmtech_k325t-template.txt: { file_type: user }

  qmtech_k325t_zyjzgw:
    files:
      - constraints/qmtech-zyjzgw.xdc: { file_type: XDC }
      - proginfo/qmtech_k325t-template.txt: { file_type: user }

  verilator:
    files:
      - verilator/chiselv.cpp: { file_type: cppSource }
      - verilator/uart.c: { file_type: cSource }

generate:
  default-chisel:
    generator: chisel
    parameters: &baseparam
      extraargs: "--board bypass --cpufreq 15000000"
      buildtool: mill
      chiselproject: chiselv
      copy_core: true
      output:
        files:
          - generated/ALU.sv: { file_type: systemVerilogSource }
          - generated/Blinky.sv: { file_type: systemVerilogSource }
          - generated/CPUSingleCycle.sv: { file_type: systemVerilogSource }
          - generated/Decoder.sv: { file_type: systemVerilogSource }
          - generated/DualPortRAM.sv: { file_type: systemVerilogSource }
          - generated/extern_modules.sv: { file_type: systemVerilogSource }
          - generated/GPIO.sv: { file_type: systemVerilogSource }
          - generated/InstructionMemory.sv: { file_type: systemVerilogSource }
          - generated/mem_2048x32.sv: { file_type: systemVerilogSource }
          - generated/mem_2048x32_0.sv: { file_type: systemVerilogSource }
          - generated/MemoryIOManager.sv: { file_type: systemVerilogSource }
          - generated/ProgramCounter.sv: { file_type: systemVerilogSource }
          - generated/Queue128_UInt8.sv: { file_type: systemVerilogSource }
          - generated/ram_128x8.sv: { file_type: systemVerilogSource }
          - generated/RegisterBank.sv: { file_type: systemVerilogSource }
          - generated/SOC.sv: { file_type: systemVerilogSource }
          - generated/Syscon.sv: { file_type: systemVerilogSource }
          - generated/Timer.sv: { file_type: systemVerilogSource }
          - generated/Toplevel.sv: { file_type: systemVerilogSource }
          - generated/Uart.sv: { file_type: systemVerilogSource }
          - generated/PLL.v: { file_type: verilogSource }
          - generated/GPIOInOut.v: { file_type: verilogSource }

  bypass:
    generator: chisel
    parameters:
      <<: *baseparam
      extraargs: "--board bypass --cpufreq 50000000 --split-verilog"

  ulx3s:
    generator: chisel
    parameters:
      <<: *baseparam
      extraargs: "--board ulx3s --cpufreq 15000000 --invreset true --split-verilog"

  artya7-35t:
    generator: chisel
    parameters:
      <<: *baseparam
      extraargs: "--board artya7-35t --cpufreq 25000000 --invreset true --split-verilog"

  qmtech_k325t:
    generator: chisel
    parameters:
      <<: *baseparam
      extraargs: "--board qmtech_k325t --cpufreq 50000000 --invreset true --split-verilog"

targets:
  lint:
    default_tool: verilator
    description: Lint the RTL. Uses Verilator by default
    filesets: [base]
    generate: [bypass]
    tools:
      verilator:
        mode: lint-only
        verilator_options: ["--timescale 1ns/1ps"]
    toplevel: Toplevel
    parameters:
      - ENABLE_INITIAL_MEM_

  verilator:
    default_tool: verilator
    description: Runs the Verilator simulation
    filesets: [base, verilator, progload]
    generate: [bypass]
    tools:
      verilator:
        mode: cc
        verilator_options: [--timescale 1ns/1ps, -O3, --assert]
    toplevel: Toplevel
    parameters:
      - ENABLE_INITIAL_MEM_

  ulx3s_85:
    default_tool: trellis
    description: ULX3S 85k version
    filesets: [base, ulx3s-85, proginfo, progload]
    generate: [ulx3s]
    hooks:
      post_run: [ulx3s-85f]
    tools:
      diamond:
        part: LFE5U-85F-6BG381C
      trellis:
        nextpnr_options: [--package, CABGA381, --85k, --lpf-allow-unconstrained]
        yosys_synth_options: [-abc9, -nowidelut]
    parameters:
      - ENABLE_INITIAL_MEM_
    toplevel: Toplevel

  artya7-35t:
    default_tool: vivado
    description: Digilent ArtyA7-35T Board using Vivado
    filesets: [base, artya7-35t, progload]
    generate: [artya7-35t]
    tools:
      vivado:
        part: xc7a35ticsg324-1L
    toplevel: Toplevel
    parameters:
      - ENABLE_INITIAL_MEM_

  artya7-35t-oss:
    default_tool: symbiflow
    description: Digilent ArtyA7-35T Board using Symbiflow OSS Toolchain
    filesets: [base, artya7-35t, proginfo, progload]
    generate: [artya7-35t]
    hooks:
      post_run: [artya7-35t]
    tools:
      symbiflow:
        part: xc7a35t
        package: csg324-1
        vendor: xilinx
        pnr: vtr
    toplevel: Toplevel
    parameters:
      - ENABLE_INITIAL_MEM_

  qmtech_k325t: &qmtech_k325t
    default_tool: xray
    description: QMTech Kintex 7 K325T Board using Project X-Ray OSS Toolchain
    filesets: [base, qmtech_k325t, proginfo, progload]
    generate: [qmtech_k325t]
    hooks:
      post_run: [qmtech_k325t]
    tools:
      xray:
        part: xc7k325t
        package: ffg676-1
        yosys_synth_options: [-abc9, -flatten]
        nextpnr_options: [--verbose, --debug]
    toplevel: Toplevel
    parameters:
      - ENABLE_INITIAL_MEM_

  qmtech_k325t_zyjzgw:
    <<: *qmtech_k325t
    description: QMTech Kintex 7 K325T ZYJZGW Board using Project X-Ray OSS Toolchain
    filesets: [base, qmtech_k325t_zyjzgw, proginfo, progload]

parameters:
  # Used by firtool so the memories are initialized with readmemh. Ref https://github.com/llvm/circt/pull/5237
  ENABLE_INITIAL_MEM_:
    datatype: bool
    default: true
    paramtype: vlogdefine

scripts:
  artya7-35t:
    cmd: [python3, proginfo.py, artya7-35t]
  ulx3s-85f:
    cmd: [python3, proginfo.py, ulx3s-85f]
  qmtech_k325t:
    cmd: [python3, proginfo.py, qmtech_k325t]