chiselv

CAPI=2:

name: carlosedp:chiselv:singlecycle:0
description : ChiselV is a RV32I core written in Chisel

filesets:
  # These are the demo filesets, use the `&demofiles` tag for the one to be used
  gpiodemo:
    files:
      - gcc/blinkLED/main-rom.mem:
          { copyto: progload.mem, file_type: user }
      - gcc/blinkLED/main-ram.mem:
          { copyto: progload-RAM.mem, file_type: user }

  uartdemo: &demofiles
    files:
      - gcc/helloUART/main-rom.mem:
          { copyto: progload.mem, file_type: user }
      - gcc/helloUART/main-ram.mem:
          { copyto: progload-RAM.mem, file_type: user }

  # This is the fileset to be programmed into the FPGA
  progload:
    <<: *demofiles

  # Show the programming info for the FPGAs
  proginfo:
    files:
      - proginfo/proginfo.py : {file_type : user, copyto : proginfo.py}
      - proginfo/boardconfig.yaml : {file_type : user, copyto : boardconfig.yaml}

  base:
    depend: ["fusesoc:utils:generators"]

  # Files specific to each FPGA board
  ulx3s-85:
    files:
      - constraints/ecp5-ulx3s.lpf: { file_type: LPF }
      - openocd/ft231x.cfg: { file_type: user }
      - openocd/LFE5U-85F.cfg: { file_type: user }
      - proginfo/ulx3s-template.txt: { file_type: user }

  artya7-35t:
    files:
      - constraints/arty_a7.xdc: { file_type: xdc }
      - openocd/digilent-hs1.cfg: { file_type: user }
      - openocd/xilinx-xc7.cfg: { file_type: user }
      - proginfo/artix7-template.txt: { file_type: user }

generate:
  default-chisel:
    generator: chisel
    parameters: &baseparam
      extraargs: "--target:fpga -board bypass -cpufreq 15000000"
      buildtool: sbt
      copy_core: true
      output:
        files:
          - generated/Toplevel.v: { file_type: verilogSource }
          - generated/GPIOInOut.v: { file_type: verilogSource }
          - generated/PLL.v: { file_type: verilogSource }

  bypass:
    generator: chisel
    parameters:
      <<: *baseparam
      extraargs: "--target:fpga -board bypass -cpufreq 15000000"

  ulx3s:
    generator: chisel
    parameters:
      <<: *baseparam
      extraargs: "--target:fpga -board ulx3s -cpufreq 15000000"

  artya7-35t:
    generator: chisel
    parameters:
      <<: *baseparam
      extraargs: "--target:fpga -board artya7-35t -cpufreq 25000000"

targets:
  lint:
    default_tool : verilator
    description : Lint the RTL. Uses Verilator by default
    filesets: [base]
    generate: [bypass]
    tools :
      verilator :
        mode : lint-only
        verilator_options: ["--timescale 1ns/1ps"]
    toplevel : Toplevel

  ulx3s_85:
    default_tool: trellis
    description: ULX3S 85k version
    filesets: [base, ulx3s-85, proginfo, progload]
    generate: [ulx3s]
    hooks:
      post_run: [ulx3s-85f]
    tools:
      diamond:
        part: LFE5U-85F-6BG381C
      trellis:
        nextpnr_options: [--package, CABGA381, --85k, --lpf-allow-unconstrained]
        yosys_synth_options: [-abc9, -nowidelut]
    toplevel: Toplevel

  artya7-35t:
    default_tool : vivado
    description: Digilent ArtyA7-35T Board using Vivado
    filesets : [base, artya7-35t, progload]
    generate: [artya7-35t]
    tools:
      vivado:
        part : xc7a35ticsg324-1L
    toplevel : Toplevel

  artya7-35t-oss:
    default_tool : symbiflow
    description: Digilent ArtyA7-35T Board using Symbiflow OSS Toolchain
    filesets : [base, artya7-35t, proginfo, progload]
    generate: [artya7-35t]
    hooks:
      post_run: [artya7-35t]
    tools:
      symbiflow:
        part : xc7a35t
        package: csg324-1
        vendor: xilinx
        pnr: vtr
    toplevel : Toplevel

scripts:
  artya7-35t:
    cmd : [python3, proginfo.py, artya7-35t]
  ulx3s-85f:
    cmd : [python3, proginfo.py, ulx3s-85f]