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{
"$schema": "http://json-schema.org/draft-07/schema#",
"$id": "http://pulp-platform.org/snitch/snitch_cluster.schema.json",
"title": "Snitch Cluster Schema",
"description": "Base description of a Snitch cluster and its internal structure and configuration.",
"type": "object",
"required": [
"addr_width",
"hives"
],
"properties": {
"name": {
"type": "string",
"description": "Optional name for the generated wrapper.",
"default": "snitch_cluster"
},
"boot_addr": {
"type": "number",
"description": "Address from which all harts of the cluster start to boot. The default setting is `0x8000_0000`.",
"default": 2147483648
},
"cluster_base_addr": {
"type": "number",
"description": "Base address of this cluster.",
"default": 0
},
"tcdm": {
"type": "object",
"description": "Configuration of the Tightly Coupled Data Memory of this cluster.",
"default": {
"size": 128,
"banks": 32
},
"properties": {
"size": {
"type": "number",
"description": "Size of TCDM in KiByte. Divided in `n` banks. The total size must be divisible by the number of banks.",
"examples": [
128,
64
]
},
"banks": {
"type": "number",
"description": "Number of banks.",
"examples": [
16,
32
]
}
}
},
"cluster_periph_size": {
"type": "number",
"description": "Address region size reserved for cluster peripherals in KiByte.",
"examples": [
128,
64
]
},
"zero_mem_size": {
"type": "number",
"description": "Address region size reserved for the Zero-Memory in KiByte.",
"examples": [
128,
64
]
},
"addr_width": {
"type": "number",
"description": "Length of the address, should be greater than 30. If the address is larger than 34 the data bus needs to be 64 bits in size.",
"default": 48
},
"data_width": {
"type": "number",
"description": "Data bus size of the integer core (everything except the DMA), must be 32 or 64. A double precision FPU requires 64 bit data length.",
"default": 64
},
"dma_data_width": {
"type": "number",
"description": "Data bus size of DMA. Usually this is larger than the integer core as the DMA is used to efficiently transfer bulk of data.",
"default": 512
},
"narrow_trans": {
"type": "number",
"description": "Outstanding transactions on the narrow AXI network",
"default": 4
},
"wide_trans": {
"type": "number",
"description": "Outstanding transactions on the wide AXI network",
"default": 4
},
"id_width_in": {
"type": "number",
"description": "Id width of the narrower AXI plug into the cluster.",
"default": 2
},
"dma_id_width_in": {
"type": "number",
"description": "Id width of the wide AXI plug into the cluster.",
"default": 1
},
"user_width": {
"type": "number",
"description": "User width of the narrower AXI plug into the cluster.",
"default": 1
},
"dma_user_width": {
"type": "number",
"description": "User width of the wide AXI plug into the cluster.",
"default": 1
},
"hart_base_id": {
"type": "number",
"description": "Base hart id of the cluster. All cores get the respective cluster id plus their cluster position as the final `hart_id`.",
"default": 0
},
"mode": {
"type": "string",
"description": "Supported mode by the processor, can be msu.",
"$comment": "Currently ignored."
},
"vm_support": {
"type": "boolean",
"description": "Whether to provide virtual memory support (Sv32).",
"default": true
},
"dma_axi_req_fifo_depth": {
"type": "number",
"description": "Number of AXI FIFO entries of the DMA engine.",
"default": 3
},
"dma_req_fifo_depth": {
"type": "number",
"description": "Number of request entries the DMA can keep",
"default": 3
},
"enable_debug": {
"type": "boolean",
"description": "Whether to provide a debug request input and external debug features",
"default": true
},
"sram_cfg_expose": {
"type": "boolean",
"description": "Whether to expose memory cut configuration inputs for implementation",
"default": false
},
"sram_cfg_fields": {
"type": "object",
"description": "The names and widths of memory cut configuration inputs needed for implementation",
"default": {"reserved" : 1},
"minProperties": 1,
"propertyNames": { "pattern": "^[A-Za-z_][A-Za-z0-9_]*$" },
"additionalProperties": { "type": "number", "minimum": 1 }
},
"timing": {
"type": "object",
"title": "Timing and Latency Tuning Parameter",
"properties": {
"iso_crossings": {
"type": "boolean",
"description": "Enable isochronous crossings, this clocks the integer core at half the speed of the rest of the system.",
"default": false
},
"narrow_xbar_latency": {
"type": "string",
"description": "Latency mode of the cluster crossbar.",
"enum": [
"NO_LATENCY",
"CUT_SLV_AX",
"CUT_MST_AX",
"CUT_ALL_AX",
"CUT_SLV_PORTS",
"CUT_MST_PORTS",
"CUT_ALL_PORTS"
],
"default": "CUT_ALL_PORTS"
},
"wide_xbar_latency": {
"type": "string",
"description": "Latency mode of the DMA crossbar.",
"enum": [
"NO_LATENCY",
"CUT_SLV_AX",
"CUT_MST_AX",
"CUT_ALL_AX",
"CUT_SLV_PORTS",
"CUT_MST_PORTS",
"CUT_ALL_PORTS"
],
"default": "CUT_ALL_PORTS"
},
"register_offload_req": {
"type": "boolean",
"description": "Insert Pipeline registers into off-loading path (request).",
"default": false
},
"register_offload_rsp": {
"type": "boolean",
"description": "Insert Pipeline registers into off-loading path (response).",
"default": false
},
"register_core_req": {
"type": "boolean",
"description": "Insert Pipeline registers into data memory request path.",
"default": false
},
"register_core_rsp": {
"type": "boolean",
"description": "Insert Pipeline registers into data memory response path.",
"default": false
},
"register_fpu_req": {
"type": "boolean",
"description": "Insert Pipeline register into the FPU request data path",
"default": false
},
"register_fpu_in": {
"type": "boolean",
"description": "Insert Pipeline registers immediately before FPU datapath",
"default": false
},
"register_fpu_out": {
"type": "boolean",
"description": "Insert Pipeline registers immediately after FPU datapath",
"default": false
},
"register_tcdm_cuts": {
"type": "boolean",
"description": "Insert Pipeline registers after each memory cut.",
"default": false
},
"register_ext_wide": {
"type": "boolean",
"description": "Decouple wide external AXI plug.",
"default": false
},
"register_ext_narrow": {
"type": "boolean",
"description": "Decouple narrow external AXI plug.",
"default": false
},
"register_sequencer": {
"type": "boolean",
"description": "Insert Pipeline registers after sequencer.",
"default": false
},
"lat_comp_fp32": {
"type": "number",
"description": "Latency setting (number of pipeline stages) for FP32.",
"default": 3
},
"lat_comp_fp64": {
"type": "number",
"description": "Latency setting (number of pipeline stages) for FP64.",
"default": 3
},
"lat_comp_fp16": {
"type": "number",
"description": "Latency setting (number of pipeline stages) for FP16.",
"default": 1
},
"lat_comp_fp16_alt": {
"type": "number",
"description": "Latency setting (number of pipeline stages) for FP16alt (brainfloat).",
"default": 2
},
"lat_comp_fp8": {
"type": "number",
"description": "Latency setting (number of pipeline stages) for FP8.",
"default": 1
},
"lat_comp_fp8alt": {
"type": "number",
"description": "Latency setting (number of pipeline stages) for FP8alt.",
"default": 1
},
"lat_noncomp": {
"type": "number",
"description": "Latency setting (number of pipeline stages) for floating-point non-computational instructions (except conversions), i.e., `classify`, etc.",
"default": 1
},
"lat_conv": {
"type": "number",
"description": "Latency setting (number of pipeline stages) for floating-point conversion instructions.",
"default": 1
},
"lat_sdotp": {
"type": "number",
"description": "Latency setting (number of pipeline stages) for floating-point expanding dot product with accumulation.",
"default": 2
},
"fpu_pipe_config": {
"type": "string",
"description": "Pipeline configuration (i.e., position of the registers) of the FPU.",
"enum": [
"BEFORE",
"AFTER",
"INSIDE",
"DISTRIBUTED"
],
"default": "BEFORE"
}
}
},
"hives": {
"type": "array",
"title": "Hives",
"description": "Cores in a hive share an instruction cache and other shared infrastructure such as the PTW or the multiply/divide unit.",
"minItems": 1,
"items": {
"type": "object",
"title": "Hive Description",
"description": "Configuration of a Hive",
"properties": {
"icache": {
"type": "object",
"title": "Hive's instruction cache configuration.",
"description": "Detailed configuration of the current Hive's instruction cache.",
"default": {
"size": 8,
"sets": 2,
"cacheline": 128
},
"properties": {
"size": {
"type": "number",
"description": "Total instruction cache size in KiByte."
},
"sets": {
"type": "number",
"description": "Number of ways."
},
"cacheline": {
"type": "number",
"description": "Cacheline/Word size in bits."
}
}
},
"cores": {
"type": "array",
"title": "Cores",
"description": "List of all cores in the respective hive.",
"minItems": 1,
"items": {
"type": "object",
"title": "Core Description",
"description": "Description of a single core.",
"properties": {
"isa": {
"type": "string",
"title": "ISA String containing RISC-V standard extensions.",
"description": "ISA string as defined by the RISC-V standard. Only contain the standardized ISA extensions.",
"examples": [
"rv32imafd"
],
"default": "rv32imafd"
},
"Xdiv_sqrt": {
"type": "boolean",
"description": "Enable hardware support for floating-point division and square-root. The iterative floating-point unit is known to produce some rounding inaccuracies so it is disabled by default.",
"default": false
},
"xssr": {
"type": "boolean",
"title": "Enable Xssr Extension",
"description": "Stream Semantic Registers (Xssr) custom extension.",
"default": true
},
"xfrep": {
"type": "boolean",
"title": "Enable Xfrep Extension",
"description": "Floating-point repetition buffer (Xfrep) custom extension.",
"default": true
},
"xdma": {
"type": "boolean",
"title": "Xdma Extension",
"description": "Direct memory access (Xdma) custom extension.",
"default": false
},
"xf8": {
"type": "boolean",
"title": "Xf8 8-bit Float Extension",
"description": "Enable Smallfloat Xf8 extension (IEEE 8-bit float).",
"default": false
},
"xf8alt": {
"type": "boolean",
"title": "Xf8 8-bit Float Extension",
"description": "Enable Smallfloat Xf8alt extension.",
"default": false
},
"xf16": {
"type": "boolean",
"title": "Xf16 16-bit Float Extension",
"description": "Enable Smallfloat Xf16 extension (IEEE 16-bit float).",
"default": false
},
"xf16alt": {
"type": "boolean",
"title": "Xf16alt 16-bit Brain-Float Extension",
"description": "Enable Smallfloat Xf16alt extension, also known as brain-float.",
"default": false
},
"xfdotp": {
"type": "boolean",
"title": "Xfdotp Extension",
"description": "Enable DOTP extensions.",
"default": false
},
"xfvec": {
"type": "boolean",
"title": "Xfvec Extension",
"description": "Enable Smallfloat vector extension (SIMD).",
"default": false
},
"num_int_outstanding_loads": {
"type": "number",
"description": "Number of outstanding integer loads. Determines the buffer size in the core's load/store unit.",
"default": 1
},
"num_int_outstanding_mem": {
"type": "number",
"description": "Number of outstanding memory operations. Determines the buffer size in the core's load/store unit.",
"default": 1
},
"num_fp_outstanding_loads": {
"type": "number",
"description": "Number of outstanding floating-point loads. Determines the buffer size in the FPU's load/store unit.",
"default": 4
},
"num_fp_outstanding_mem": {
"type": "number",
"description": "Number of outstanding memory operations. Determines the buffer size in the core's load/store unit.",
"default": 1
},
"num_sequencer_instructions": {
"type": "number",
"description": "Amount of floating-point instruction the floating-point sequence buffer can hold.",
"default": 16
},
"num_itlb_entries": {
"type": "number",
"description": "Number of ITLB entries. Determines the core's size.",
"default": 1
},
"num_dtlb_entries": {
"type": "number",
"description": "Number of DTLB entries. Determines the core's size.",
"default": 2
},
"ssr_intersection": {
"type": "boolean",
"title": "SSR Intersection Feature",
"description": "Enable intersection between 3 SSRs for sparse-sparse processing.",
"default": false
},
"ssr_intersection_triple": {
"type": "array",
"title": "SSR Intersection Triple",
"description": "Indices of the SSRs forming an SSR intersection triple.",
"maxItems": 3,
"minItems": 3,
"default": [0, 1, 2],
"items": {
"type": "number"
}
},
"ssr_mux_resp_depth": {
"type": "number",
"description": "Depth of response buffer in the TCDM multiplexer arbitrating between core and SSR 0.",
"default": 4
},
"ssrs": {
"type": "array",
"title": "SSRs",
"description": "List of all SSRs in the respective core.",
"minItems": 0,
"default": [{}, {}, {}],
"items": {
"type": "object",
"title": "SSR Description",
"description": "Description of a single Stream Semantic Register.",
"properties": {
"reg_idx": {
"type": ["number", "null"],
"description": "The floating-point register index this SSR is assigned to. If not assigned, the next available index counting from 0 is chosen.",
"minimum": 0,
"maximum": 31,
"default": null
},
"indirection": {
"type": "boolean",
"description": "Enable indirection extension.",
"default": false
},
"indir_out_spill": {
"type": "boolean",
"description": "Whether to cut timing paths with a spill register at the address generator output; added only if indirection extension enabled.",
"default": true
},
"isect_slave_spill": {
"type": "boolean",
"description": "Whether to cut timing paths with a spill register at the intersector index output; added only if this SSR is an intersection slave.",
"default": true
},
"isect_slave_credits": {
"type": "number",
"description": "Number of elements by which intersected indices may outrun corresponding data; added only if this SSR is an intersection slave.",
"minimum": 2,
"default": 8
},
"num_loops": {
"type": "number",
"description": "Number of nested hardware loops in address generator.",
"minimum": 1,
"maximum": 4,
"default": 4
},
"index_credits": {
"type": "number",
"description": "Number of credits and buffer depth of the index word FIFO.",
"minimum": 1,
"default": 3
},
"data_credits": {
"type": "number",
"description": "Number of credits and buffer depth of the data word FIFO.",
"minimum": 1,
"default": 4
},
"mux_resp_depth": {
"type": "number",
"description": "Depth of response buffer in the TCDM multiplexer arbitrating between data and indices.",
"minimum": 1,
"default": 3
},
"index_width": {
"type": ["number", "null"],
"description": "Internal bitwidth of indices in address generator; default covers full TCDM in a unit-stride 1D loop.",
"minimum": 1,
"maximum": 32,
"default": null
},
"pointer_width": {
"type": ["number", "null"],
"description": "Internal bitwidth of pointers in address generator; default covers full TCDM",
"maximum": 32,
"default": null
},
"shift_width": {
"type": "number",
"description": "Internal bitwidth of additional left shift amount for indirect indices.",
"minimum": 1,
"maximum": 32,
"default": 3
},
"rpt_width": {
"type": "number",
"description": "Internal bitwidth of repetition counter for read streams.",
"minimum": 1,
"maximum": 32,
"default": 4
}
}
}
}
}
}
}
}
}
}
}
}
a480b9028This file is pinned to the selected release. Download the original to open it in your design tool.