snitch

{"$schema":"http://json-schema.org/draft-07/schema#","$id":"http://pulp-platform.org/snitch/occamy.schema.json","title":"Occamy System Schema","description":"Description of an Occamy-based system.","type":"object","required":["cluster"],"properties":{"cluster":{"$ref":"http://pulp-platform.org/snitch/snitch_cluster.schema.json"},"quadrant_pre_xbar":{"$ref":"http://pulp-platform.org/snitch/axi_xbar.schema.json"},"pre_xbar_slv_id_width_no_rocache":{"type":"integer","description":"ID width of quadrant pre-crossbar slave ports assuming no read-only cache.","default":3},"wide_xbar":{"$ref":"http://pulp-platform.org/snitch/axi_xbar.schema.json"},"quadrant_inter_xbar":{"$ref":"http://pulp-platform.org/snitch/axi_xbar.schema.json"},"hbm_xbar":{"$ref":"http://pulp-platform.org/snitch/axi_xbar.schema.json"},"narrow_xbar":{"$ref":"http://pulp-platform.org/snitch/axi_xbar.schema.json"},"narrow_xbar_slv_id_width":{"type":"integer","description":"ID width of narrow crossbar slave ports.","default":4},"nr_s1_quadrant":{"title":"Number of S1 Quadrants","type":"integer","default":8},"narrow_tlb_cfg":{"$ref":"http://pulp-platform.org/snitch/axi_tlb.schema.json"},"wide_tlb_cfg":{"$ref":"http://pulp-platform.org/snitch/axi_tlb.schema.json"},"cuts":{"title":"Number of cuts on the AXI bus","type":"object","properties":{"narrow_to_quad":{"type":"integer","description":"narrow xbar -> quad","default":3},"quad_to_narrow":{"type":"integer","description":"quad -> narrow xbar","default":3},"quad_to_pre":{"type":"integer","description":"quad -> pre xbar","default":1},"pre_to_inter":{"type":"integer","description":"pre xbar -> inter xbar","default":1},"inter_to_quad":{"type":"integer","description":"inter xbar -> quad","default":3},"narrow_to_cva6":{"type":"integer","description":"narrow -> cva6","default":1},"narrow_conv_to_spm_narrow_pre":{"type":"integer","description":"narrow -> SPM pre atomic adapter","default":1},"narrow_conv_to_spm_narrow":{"type":"integer","description":"narrow -> SPM post atomic adapter","default":1},"narrow_and_pcie":{"type":"integer","description":"PCIe in and out","default":1},"narrow_and_wide":{"type":"integer","description":"narrow xbar -> wide xbar & wide xbar -> narrow xbar","default":0},"wide_conv_to_spm_wide":{"type":"integer","description":"wide xbar -> wide spm","default":1},"wide_to_wide_zero_mem":{"type":"integer","description":"wide xbar -> wide zero memory","default":0},"wide_to_hbm":{"type":"integer","description":"wide xbar -> hbm xbar","default":6},"wide_and_inter":{"type":"integer","description":"inter xbar -> wide xbar & wide xbar -> inter xbar","default":3},"wide_and_hbi":{"type":"integer","description":"hbi <-> wide xbar","default":3},"narrow_and_hbi":{"type":"integer","description":"hbi <-> narrow xbar","default":3},"pre_to_hbmx":{"type":"integer","description":"pre xbar -> hbm xbar","default":3},"hbmx_to_hbm":{"type":"integer","description":"hbmx -> hbm","default":3},"atomic_adapter_narrow":{"type":"integer","description":"narrow spm atomic adapter internal cuts","default":1},"atomic_adapter_narrow_wide":{"type":"integer","description":"narrow_to_wide atomic adapter internal cuts","default":1},"periph_axi_lite_narrow":{"type":"integer","description":"soc narrow -> periph regbus","default":3},"periph_axi_lite":{"type":"integer","description":"soc narrow -> periph axilite","default":3},"periph_axi_lite_narrow_hbm_xbar_cfg":{"type":"integer","description":"axi lite narrow cuts before regbus translation for hbm_xbar_cfg","default":3},"periph_axi_lite_narrow_hbi_wide_cfg":{"type":"integer","description":"axi lite narrow cuts before regbus translation for hbi_wide_cfg","default":3},"periph_axi_lite_narrow_hbi_narrow_cfg":{"type":"integer","description":"axi lite narrow cuts before regbus translation for hbi_narrow_cfg","default":3},"periph_axi_lite_narrow_pcie_cfg":{"type":"integer","description":"axi lite narrow cuts before regbus translation for pcie_cfg","default":2},"periph_axi_lite_narrow_hbm_cfg":{"type":"integer","description":"axi lite narrow cuts before regbus translation for hbm_cfg","default":3},"periph_axi_lite_narrow_clint_cfg":{"type":"integer","description":"axi lite narrow cuts before regbus translation for clint_cfg","default":1},"periph_axi_lite_narrow_soc_ctrl_cfg":{"type":"integer","description":"axi lite narrow cuts before regbus translation for soc_ctrl_cfg","default":1},"periph_axi_lite_narrow_chip_ctrl_cfg":{"type":"integer","description":"axi lite narrow cuts before regbus translation for chip_ctrl_cfg","default":1},"periph_axi_lite_narrow_uart_cfg":{"type":"integer","description":"axi lite narrow cuts before regbus translation for uart_cfg","default":2},"periph_axi_lite_narrow_bootrom_cfg":{"type":"integer","description":"axi lite narrow cuts before regbus translation for bootrom_cfg","default":3},"periph_axi_lite_narrow_fll_system_cfg":{"type":"integer","description":"axi lite narrow cuts before regbus translation for fll_system_cfg","default":3},"periph_axi_lite_narrow_fll_periph_cfg":{"type":"integer","description":"axi lite narrow cuts before regbus translation for fll_periph_cfg","default":3},"periph_axi_lite_narrow_fll_hbm2e_cfg":{"type":"integer","description":"axi lite narrow cuts before regbus translation for fll_hbm2e_cfg","default":3},"periph_axi_lite_narrow_plic_cfg":{"type":"integer","description":"axi lite narrow cuts before regbus translation for plic_cfg","default":1},"periph_axi_lite_narrow_spim_cfg":{"type":"integer","description":"axi lite narrow cuts before regbus translation for spim_cfg","default":32},"periph_axi_lite_narrow_gpio_cfg":{"type":"integer","description":"axi lite narrow cuts before regbus translation for gpio_cfg","default":2},"periph_axi_lite_narrow_i2c_cfg":{"type":"integer","description":"axi lite narrow cuts before regbus translation for i2c_cfg","default":2},"periph_axi_lite_narrow_timer_cfg":{"type":"integer","description":"axi lite narrow cuts before regbus translation for timer_cfg","default":1}}},"txns":{"title":"Number of outstanding transactions on the AXI bus","type":"object","properties":{"wide_and_inter":{"type":"integer","description":"inter xbar -> wide xbar & wide xbar -> inter xbar","default":4},"wide_to_hbm":{"type":"integer","description":"wide xbar -> hbm xbar","default":4},"narrow_and_wide":{"type":"integer","description":"narrow xbar -> wide xbar & wide xbar -> narrow xbar","default":4},"rmq":{"type":"integer","description":"Remote Quadrant mux/demux","default":4}}},"is_remote_quadrant":{"description":"Set if this is a remote quadrant. Only quadrant ant remote interconnect is generated","type":"boolean","default":false},"remote_quadrants":{"title":"Remote Quadrants","type":"array","description":"List of attached remote quadrants","minItems":0,"items":{"type":"object","title":"Remote Quadrant Description","description":"Description of a remote quadrant","properties":{"nr_clusters":{"type":"integer","default":4,"description":"Number of clusters in an S1 quadrant."},"nr_cluster_cores":{"type":"integer","default":8,"description":"Number of cores in a cluster"}}}},"s1_quadrant":{"title":"S1 Quadrant Properties","type":"object","properties":{"nr_clusters":{"type":"integer","default":4,"description":"Number of clusters in an S1 quadrant."},"ro_cache_cfg":{"type":"object","description":"Constant cache configuration.","properties":{"max_trans":{"type":"integer","description":"Maximum Outstanding Transaction","default":4},"width":{"type":"integer","description":"Cache Line Width"},"count":{"type":"integer","description":"The number of cache lines per set. Power of two; >= 2."},"sets":{"type":"integer","description":"The set associativity of the cache. Power of two; >= 1."},"address_regions":{"type":"integer","description":"Number of programmable address regions.","default":1}}},"wide_xbar":{"$ref":"http://pulp-platform.org/snitch/axi_xbar.schema.json"},"wide_xbar_slv_id_width":{"type":"integer","description":"ID width of wide quadrant crossbar slave ports.","default":3},"narrow_xbar":{"$ref":"http://pulp-platform.org/snitch/axi_xbar.schema.json"},"narrow_xbar_slv_id_width":{"type":"integer","description":"ID width of narrow quadrant crossbar slave ports.","default":4},"cfg_base_addr":{"type":"integer","description":"Base address of the quadrant configuration region.","default":184549376},"cfg_base_offset":{"type":"integer","description":"Allocated size and offset of each quadrant configuration.","default":65536}}},"spm_narrow":{"$ref":"http://pulp-platform.org/snitch/address_range.schema.json"},"spm_wide":{"$ref":"http://pulp-platform.org/snitch/address_range.schema.json"},"wide_zero_mem":{"$ref":"http://pulp-platform.org/snitch/address_range.schema.json"},"pcie":{"title":"Configuration of external PCIe port","type":"object","properties":{"address_io":{"type":"integer","description":"Base address of PCIe IO range.","minimum":0},"address_mm":{"type":"integer","description":"Base address of PCIe memory-mapped range.","minimum":0},"length":{"type":"integer","description":"Size in bytes of all PCIe ranges.","minimum":0}}},"hbi":{"$ref":"http://pulp-platform.org/snitch/address_range.schema.json"},"hbm":{"title":"Configuration of external HBM interface","type":"object","properties":{"address_1":{"type":"integer","description":"Start of HBM address region 1.","minimum":0},"address_2":{"type":"integer","description":"Start of HBM address region 1.","minimum":0},"channel_size":{"type":"integer","description":"Size of single HBM channel region.","minimum":0},"nr_channels_total":{"type":"integer","description":"Total number of HBM channels.","minimum":0},"nr_channels_address_0":{"type":"integer","description":"Number of lower HBM channels accessible over address region 1","minimum":0},"cfg_regions":{"properties":{"top":{"$ref":"http://pulp-platform.org/snitch/address_range.schema.json"},"phy":{"$ref":"http://pulp-platform.org/snitch/address_range.schema.json"},"seq":{"$ref":"http://pulp-platform.org/snitch/address_range.schema.json"},"ctrl":{"$ref":"http://pulp-platform.org/snitch/address_range.schema.json"}}}}},"peripherals":{"$ref":"http://pulp-platform.org/snitch/peripherals.schema.json"}}}