serv

CAPI=2:

name : award-winning:serv:serv:1.4.0
description: The award-winning SERV, the world's smallest RISC-V CPU
license: ISC

filesets:
  core:
    files:
      - "tool_verilator? (data/verilator_waiver.vlt)" : {file_type: vlt}
      - rtl/serv_bufreg.v
      - rtl/serv_bufreg2.v
      - rtl/serv_alu.v
      - rtl/serv_csr.v
      - rtl/serv_ctrl.v
      - rtl/serv_decode.v
      - rtl/serv_immdec.v
      - rtl/serv_mem_if.v
      - rtl/serv_rf_if.v
      - rtl/serv_rf_ram_if.v
      - rtl/serv_rf_ram.v
      - rtl/serv_state.v
      - rtl/serv_debug.v
      - rtl/serv_top.v
      - rtl/serv_rf_top.v
      - rtl/serv_aligner.v
      - rtl/serv_compdec.v
    file_type : verilogSource

  openlane:
    files:
      - data/params.tcl : {file_type : tclSource}
      - rtl/serv_synth_wrapper.v : {file_type : verilogSource}

  verilator_decoder_tb:
    files:
      - bench/decoder_sim.v
      - "bench/decoder_tb.cpp" : {file_type : cppSource}
    file_type : verilogSource

  decoder_tb:
    files:
      - bench/decoder_sim.v
      - bench/decoder_tb.v
    file_type : verilogSource
    depend : [vlog_tb_utils]

targets:
  default:
    filesets : [core]
    parameters :
      - "is_toplevel? (ALIGN)"
      - "is_toplevel? (COMPRESSED)"
      - "is_toplevel? (MDU)"
      - "is_toplevel? (PRE_REGISTER)"
      - "is_toplevel? (RESET_STRATEGY)"
      - RISCV_FORMAL
      - SERV_CLEAR_RAM
      - "is_toplevel? (WITH_CSR)"
      - "is_toplevel? (W)"
    toplevel : ["is_toplevel? (serv_rf_top)"]

  lint:
    default_tool : verilator
    description: Run static code checks (linting)
    filesets : [core]
    parameters: [W]
    tools:
      verilator:
        mode : lint-only
        verilator_options:
          - "-Wall"
    toplevel : serv_rf_top

  sky130:
    default_tool : openlane
    description: Create GDSII for SkyWater 130nm using OpenLANE
    filesets : [core, openlane]
    toplevel : serv_synth_wrapper

  verilator_decoder_tb:
    description: Verilator decoder testbench
    filesets : [core, verilator_decoder_tb]
    flow: sim
    flow_options:
      tool: verilator
      verilator_options : [--trace]
    parameters :
      - RISCV_FORMAL
      - "mdu? (MDU=1)"
    toplevel : decoder_sim

parameters:
  MDU:
    datatype   : int
    description: Enables interface for RISC-V standard M-extension
    paramtype  : vlogparam

  PRE_REGISTER:
    datatype    : int
    description : Register signals before or after the decoder
    paramtype   : vlogparam

  RESET_STRATEGY:
    datatype : str
    paramtype : vlogparam

  RISCV_FORMAL:
    datatype  : bool
    paramtype : vlogdefine

  SERV_CLEAR_RAM:
    datatype  : bool
    paramtype : vlogdefine

  WITH_CSR:
    datatype  : int
    paramtype : vlogparam
  
  COMPRESSED:
    datatype    : int
    description : Enable/Disable the support for Compressed instructions
    paramtype   : vlogparam
  
  ALIGN:
    datatype    : int
    paramtype   : vlogparam
    description : Enable/Disable the support of misaligned instructions

  W:
    datatype    : int
    description : Internal datapath width (1=SERV, 4=QERV)
    paramtype   : vlogparam