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INSN_RESET_VECTOR: 0x0000_1000
PC_GOAL: 0x8000_1004
memory_map:
physical_address_width: 24
pc:
narrow: false
width: 19
regions:
rom:
type: memory
name: Section 0 (ROM)
logical_base: 0x0000_1000
physical_base: 0x0_0000
size: 0x0000_f000
translation: low_bits
uncachable: false
constants:
logical_prefix: LOG_ADDR_SECTION_0
physical_prefix: PHY_ADDR_SECTION_0
ram:
type: memory
name: Section 1 (RAM)
logical_base: 0x8000_0000
physical_base: 0x1_0000
size: 0x0004_0000
translation: low_bits
uncachable: false
constants:
logical_prefix: LOG_ADDR_SECTION_1
physical_prefix: PHY_ADDR_SECTION_1
uncachable:
type: memory
name: Uncachable section (RAM)
logical_base: 0x8004_0000
physical_base: 0x1_0000
size: 0x0001_0000
translation: low_bits
uncachable: true
constants:
logical_prefix: LOG_ADDR_UNCACHABLE
physical_prefix: PHY_ADDR_UNCACHABLE
serial:
type: io
name: Serial IO
logical_base: 0x4000_2000
physical_base: 0x0_2000
size: 1
translation: low_bits
constants:
logical_prefix: LOG_ADDR_SERIAL
physical_prefix: PHY_ADDR_SERIAL
registers:
OUTPUT: 0
clint:
type: io
name: CLINT
logical_base: 0x4001_0000
physical_base: 0x0_0000
size: 0x8000
translation: low_bits
constants:
logical_prefix: LOG_ADDR_CLINT
physical_prefix: PHY_ADDR_CLINT
registers:
MSIP: 0
TIMER_LOW: 0x7ff8
TIMER_HI: 0x7ffc
TIMER_CMP_LOW: 0x4000
TIMER_CMP_HI: 0x4004
plic:
type: io
name: PLIC
logical_base: 0xc000_0000
physical_base: 0x01_0000
size: 0x20_2000 # only 2 contexts
translation: low_bits
constants:
logical_prefix: LOG_ADDR_PLIC
physical_prefix: PHY_ADDR_PLIC
registers:
SOURCE_PRIORITY_BASE: 0x0
PENDING_BASE: 0x1000
ENABLE_BASE: 0x2000
PRIORITY_THRESHOLD_BASE: 0x200000
CLAIM_COMPLETE_BASE: 0x20000492595157eThis file is pinned to the selected release. Download the original to open it in your design tool.