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%
% This is rather horrible LaTeX-code as there are plenty of explicit
% \vspace*{...}. This became necessary as there is not much maneuvering
% space on a double sided leaflet for so many tables as we need here.
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% 04/05-MAY-2016 Bernd Ulmann
%
\documentclass{leaflet}
\usepackage{longtable}
\begin{document}
\title{QNICE programming card}
\maketitle
%
\section{General}
QNICE features 16 bit words, 16 registers, 4 addressing modes, and
a 16 bit address space (16 bit words, upper 256 words reserved for
memory mapped I/O).
\vspace*{-5mm}
%
\section{Registers}
All in all there are 16 general purpose registers (\emph{GPR}s) available:
\begin{center}
\vspace*{-2mm}
\begin{longtable}{|c|c|c||c|c|c|c|c|}
\hline
{\tt R0}&\dots&{\tt R7}&{\tt R8}&\dots&{\tt R13}&{\tt R14}&{\tt R15}\\
\hline
\end{longtable}
\vspace*{-9mm}
\end{center}
\begin{description}
\item [\texttt{R0}\dots\texttt{R7}:] GPRs, actually
these are a window into a register bank holding $256\times 8$ such
registers.
\item [\texttt{R13}:] Stack pointer (\texttt{SP}).
\item [\texttt{R14}:] Statusregister (\texttt{SR}).
\item [\texttt{R15}:] Program counter (\texttt{PC}).
\end{description}
%
\subsection{Statusregister}
\begin{center}
\begin{longtable}{|c||c|c|c|c|c|c|c|c|}
\hline
{\tt rbank}&
---&---&{\tt V}&{\tt N}&{\tt Z}&{\tt C}&{\tt X}&{\tt 1}\\
\hline
\end{longtable}
\vspace*{-9mm}
\end{center}
\begin{description}
\item [{\tt 1}:] Always set to 1.
\item [{\tt X}:] 1 if the last result was {\tt 0xFFFF}.
\item [{\tt C}:] Carry flag.
\item [{\tt Z}:] 1 if the last result was {\tt 0x0000}.
\item [{\tt N}:] 1 if the last result was negative.
\item [{\tt V}:] 1 if the last operation caused an overflow, i.\,e. two
positive operands yielded a negative result or vice versa.
\end{description}
The upper eight bits of \texttt{SR} hold the pointer to the register
window. Changing the value stored here will yield a different set of
GPRs \texttt{R0}\dots\texttt{R7} which is especially useful for subroutine
calls (a stack of registers, so to speak).
\vspace*{-5mm}
%
\section{Instruction Set}
QNICE features 14 basic instructions, four jump/branch instructions, three
control instructions, and four adressing modes.
\vspace*{-3mm}
{\scriptsize
\begin{center}
\begin{longtable}{|c|ll|l|}
\hline
$\!\!\!$Opc$\!\!\!$&Instr&Operands&Effect\\
\hline
\hline
{\tt 0}&{\tt MOVE}&{\tt src, dst}&{\tt dst := src}\\
{\tt 1}&{\tt ADD}&{\tt src, dst}&{\tt dst := dst + src}\\
{\tt 2}&{\tt ADDC}&{\tt src, dst}&{\tt dst := dst + src + C}\\
{\tt 3}&{\tt SUB}&{\tt src, dst}&{\tt dst := dst - src}\\
{\tt 4}&{\tt SUBC}&{\tt src, dst}&{\tt dst := dst - src - C}\\
{\tt 5}&{\tt SHL}&{\tt src, dst}&{\tt dst << src}, fill with X, shift to C\\
{\tt 6}&{\tt SHR}&{\tt src, dst}&{\tt dst >> src}, fill with C, shift to X\\
{\tt 7}&{\tt SWAP}&{\tt src, dst}&{\tt dst := ((src << 8) \& 0xFF00) |}\\
& & &~~~~~~~~~~{\tt ((src >> 8) \& 0xFF)}\\
{\tt 8}&{\tt NOT}&{\tt src, dst}&{\tt dst := !src}\\
{\tt 9}&{\tt AND}&{\tt src, dst}&{\tt dst := dst \& src}\\
{\tt A}&{\tt OR}&{\tt src, dst}&{\tt dst := dst | src}\\
{\tt B}&{\tt XOR}&{\tt src, dst}&{\tt dst := dst \^\ src}\\
{\tt C}&{\tt CMP}&{\tt src, dst}&compare {\tt src} with {\tt dst}\\
{\tt D}&reserved&&\\
{\tt E}&{\tt HALT}&&Halt the processor\\
{\tt E}&{\tt RTI}&&Return from interrupt\\
{\tt E}&{\tt INT}&dst&Issue software interrupt\\
{\tt E}&{\tt INCRB}&&Increment register bank address\\
{\tt E}&{\tt DECRB}&&Decrement register bank address\\
{\tt F}&{\tt ABRA}&{\tt dest, [!]cond}&Absolute branch\\
{\tt F}&{\tt ASUB}&{\tt dest, [!]cond}&Absolut subroutine call\\
{\tt F}&{\tt RBRA}&{\tt dest, [!]cond}&Relative branch\\
{\tt F}&{\tt RSUB}&{\tt dest, [!]cond}&Relative subroutine call\\
\hline
\end{longtable}
\end{center}
}
%
\subsection{Basic Instructions (opcodes \texttt{0}..\texttt{C})}
\begin{center}
\begin{longtable}{|c||c|c||c|c|}
\hline
4 bit&4 bit&2 bit&4 bit&2 bit\\
{\tt opcode}&{\tt src rxx}&{\tt src mode}&
{\tt dst rxx}&{\tt dst mode}\\
\hline
\end{longtable}
\end{center}
\vspace*{-14mm}
%
\subsection{Control instructions}
\begin{center}
\begin{longtable}{|c||c||c|c|}
\hline
4 bit&6 bit&4 bit&2 bit\\
{\tt opcode=E}&command&\texttt{dst rxx}&\texttt{dst mode}\\
\hline
\end{longtable}
\end{center}
\vspace*{-13mm}
%
\subsection{Jumps and Branches}
{\scriptsize
\begin{center}
\begin{longtable}{|c||c|c||c||c|c|}
\hline
4 bit&4 bit&2 bit&2 bit&1 bit&3 bit\\
& & & &{\tt negate}&{\tt select}\\
{\tt opcode=F}&{\tt src rxx}&{\tt src mode}&
{\tt mode}&{\tt condition}&{\tt condition}\\
\hline
\end{longtable}
\end{center}
}
\vspace*{-13mm}
%
\subsection{CMP}
The CMP (compare) instruction can be used for signed as well as for unsigned
comparisons:
\begin{center}
\vspace*{-2mm}
\begin{longtable}{|l|l|l|l|l|}
\hline
Condition&\multicolumn{4}{|c|}{Flags}\\
&\multicolumn{2}{|c|}{unsigned}&\multicolumn{2}{|c|}{signed}\\
&\texttt{Z}&\texttt{N}&\texttt{Z}&\texttt{V}\\
\hline
\hline
\texttt{src}$<$\texttt{dst}&\texttt{0}&\texttt{0}&\texttt{0}&\texttt{0}\\
\texttt{src}$=$\texttt{dst}&\texttt{1}&\texttt{0}&\texttt{1}&\texttt{0}\\
\texttt{src}$>$\texttt{dst}&\texttt{0}&\texttt{1}&\texttt{0}&\texttt{1}\\
\hline
\end{longtable}
\vspace*{-8mm}
\end{center}
%
\subsection{Addressing Modes}
{\scriptsize
\begin{center}
\begin{longtable}{|c|l|l|}
\hline
Mode bits&Notation&Description\\
\hline
\hline
{\tt 00}&{\tt Rxx}&Use Rxx as operand\\
{\tt 01}&{\tt @Rxx}&Use the memory cell addressed by\\
& &the contents of Rxx as operand\\
{\tt 10}&{\tt @Rxx++}&Use the memory cell addressed by\\
& &the contents of Rxx as operand and\\
& &then increment Rxx\\
{\tt 11}&{\tt @--Rxx}&Decrement Rxx and then use the\\
& &memory cell addressed by Rxx as\\
& &operand\\
\hline
\end{longtable}
\end{center}
}
\vspace*{-10mm}
%
\subsection{Shortcuts}
The file \texttt{sysdef.asm} (part of the monitor) defines some shortcuts
which facilitate write- and readability of QNICE assembler code:
\vspace*{-3mm}
\begin{center}
\begin{longtable}{|l|l|}
\hline
Shortcut&Implementation\\
\hline
\hline
\texttt{RET}&\texttt{MOVE @R13++, R15}\\
\texttt{NOP}&\texttt{ABRA R15, 1}\\
\texttt{SYSCALL(x, y)}&\texttt{ASUB x, y}\\
\hline
\texttt{SP}&\texttt{R13}\\
\texttt{SR}&\texttt{R14}\\
\texttt{PC}&\texttt{R15}\\
\hline
\end{longtable}
\end{center}
\vspace*{-15mm}
%
\section{Interrupts}
In case of a hardware interrupt, the processor expects the address of the
interrupt service routine (ISR) on the data bus. In case of a software
interrupt (\texttt{INT}-instruction) the ISR address is specified by the
\texttt{dst} part of the instruction. When an interrupt occurs, the CPU
saves the contents of \texttt{PC} and \texttt{SP} in two shadow-registers
which are not software accessible. An ISR must be left with the
\texttt{RTI}-instruction. Interrupts can not be nested.
%
\section{Input/Output}
I/O devices are memory mapped, their respective control and data registers
occupy the topmost 256 words of memory.
{\scriptsize
\begin{center}
\begin{longtable}{|l|l|l|}
\hline
Label&Address&Description\\
\hline
\hline
\texttt{IO\$BASE}&\texttt{0xFF00}&Start of I/O area\\
\hline
\texttt{IO\$SWITCH\_REG}&\texttt{0xFF00}&Switch register\\
\texttt{IO\$TIL\_DISPLAY}&\texttt{0xFF01}&TIL-display\\
\texttt{IO\$TIL\_MASK}&\texttt{0xFF02}&Mask register\\
\texttt{IO\$KBD\_STATE}&\texttt{0xFF03}&USB-keyboard state\\
\texttt{IO\$KBD\_DATA}&\texttt{0xFF04}&USB-keyboard data\\
\hline
\texttt{IO\$CYC\_LO}&\texttt{0xFF08}&Cycle counter low\\
\texttt{IO\$CYC\_MID}&\texttt{0xFF09}&Cycle counter middle\\
\texttt{IO\$CYC\_HI}&\texttt{0xFF0A}&Cycle counter high\\
\texttt{IO\$CYC\_STATE}&\texttt{0xFF0B}&Cycle counter status\\
\texttt{IO\$INS\_LO}&\texttt{0xFF0C}&Cycle counter low\\
\texttt{IO\$INS\_MID}&\texttt{0xFF0D}&Cycle counter middle\\
\texttt{IO\$INS\_HI}&\texttt{0xFF0E}&Cycle counter high\\
\texttt{IO\$INS\_STATE}&\texttt{0xFF0F}&Cycle counter status\\
\hline
\texttt{IO\$UART\_MR1x}&\texttt{0xFF10}&UART status register\\
\texttt{IO\$UART\_SRA}&\texttt{0xFF11}&UART status register\\
\texttt{IO\$UART\_RHRA}&\texttt{0xFF12}&UART receive register\\
\texttt{IO\$UART\_THRA}&\texttt{0xFF13}&UART receive register\\
\hline
\texttt{IO\$EAE\_OPERAND\_0}&\texttt{0xFF18}&EAE 1st operand\\
\texttt{IO\$EAE\_OPERAND\_1}&\texttt{0xFF19}&EAE 2nd operand\\
\texttt{IO\$EAE\_RESULT\_LO}&\texttt{0xFF1A}&EAE low result\\
\texttt{IO\$EAE\_RESULT\_HI}&\texttt{0xFF1B}&EAE high result\\
\texttt{IO\$EAE\_CSR}&\texttt{0xFF1C}&EAE command \& status reg.\\
\hline
\texttt{IO\$SD\_ADDR\_LO}&\texttt{0xFF20}&SD card low addr.\\
\texttt{IO\$SD\_ADDR\_HI}&\texttt{0xFF21}&SD card high addr.\\
\texttt{IO\$SD\_ADDR\_POS}&\texttt{0xFF22}&Ptr. to 512 byte bfr.\\
\texttt{IO\$SD\_DATA}&\texttt{0xFF23}&Byte in 512 byte bfr.\\
\texttt{IO\$SD\_ERROR}&\texttt{0xFF24}&Error code\\
\texttt{IO\$SD\_CSR}&\texttt{0xFF25}&Command and status reg.\\
\hline
\texttt{IO\$TIMER\_0\_PRE}&\texttt{0xFF28}&Timer 0 prescaler\\
\texttt{IO\$TIMER\_0\_CNT}&\texttt{0xFF28}&Timer 0 counter\\
\texttt{IO\$TIMER\_0\_INT}&\texttt{0xFF28}&Timer 0 ISR addr.\\
\texttt{IO\$TIMER\_1\_PRE}&\texttt{0xFF28}&Timer 1 prescaler\\
\texttt{IO\$TIMER\_1\_CNT}&\texttt{0xFF28}&Timer 1 counter\\
\texttt{IO\$TIMER\_1\_INT}&\texttt{0xFF28}&Timer 1 ISR addr.\\
\hline
\texttt{VGA\$STATE}&\texttt{0xFF30}&VGA status register\\
\texttt{VGA\$CR\_X}&\texttt{0xFF31}&Cursor X-position\\
\texttt{VGA\$CR\_Y}&\texttt{0xFF32}&Cursor y-position\\
\texttt{VGA\$CHAR}&\texttt{0xFF33}&Character code\\
\texttt{VGA\$OFFS\_DISPLAY}&\texttt{0xFF34}&Display RAM offset\\
\texttt{VGA\$OFFS\_RW}&\texttt{0xFF35}&R/W RAM offset\\
\texttt{VGA\$HDMI\_H\_MIN}&\texttt{0xFF36}&HDMI min. valid col.\\
\texttt{VGA\$HDMI\_H\_MAX}&\texttt{0xFF36}&HDMI max. valid col.\\
\texttt{VGA\$HDMI\_V\_MAX}&\texttt{0xFF36}&HDMI max. valid row\\
\hline
\end{longtable}
\end{center}
}
%
%\pagebreak%LAYOUT
\subsection{VGA Controller}
\subsubsection{\texttt{VGA\$STATE Bits}}
~
\vspace*{-4mm}
\begin{center}
\begin{longtable}{|l|l|}
\hline
Bit&Description\\
\hline
\hline
11&Enable R/W offset register if set.\\
10&Enable display offset register if set.\\
9&Busy (wait for 0 before issuing command).\\
8&Clear screen (set until completion).\\
7&Enable VGA controller.\\
6&Enable hardware cursor.\\
5&Enable hardware cursor blinking.\\
4&Hardware cursor mode:\\
&Small if set, large if cleared.\\
2\dots 0&Display color (RGB).\\
\hline
\end{longtable}
\end{center}
\vspace*{-15mm}
\subsubsection{\texttt{VGA\$CR\_X}}
X coordinate of next char to be displayed.
\vspace*{-8mm}
\subsubsection{\texttt{VGA\$CR\_Y}}
Y coordinate of next char to be displayed.
\vspace*{-8mm}
\subsubsection{\texttt{VGA\$CHAR}}
Writing a byte to this register causes it to be displayed on the current
X/Y coordinate on the screen. Reading from this register yields the
character at the current display coordinate.
\vspace*{-5mm}
\subsubsection{\texttt{VGA\$OFFS\_DISPLAY}}
This register holds the offset in bytes that is to be used when displaying
the video RAM. To scroll one line forward, simply add \texttt{0x0050} to
this register. For this to work, bit 10 in \texttt{VGA\$STATE} has to be
set.
\vspace*{-5mm}
\subsubsection{\texttt{VGA\$OFFS\_RW}}
Similar to \texttt{VGA\$OFFS\_DISPLAY} -- controls the offset for
read/write accesses to the display memory.
\subsection{USB-Keyboard}
\subsubsection{\texttt{IO\$KBD\_STATE}}
\begin{center}
\vspace*{-3mm}
\begin{longtable}{|l|l|}
\hline
Bit&Description\\
\hline
\hline
0&Set if an unread character is available.\\
1&Key pressed (val in bits \texttt{15..8}\\
2\dots 4&Keyboard layout:\\
&\texttt{000}: US keyboard\\
&\texttt{001}: German keyboard\\
5\dots 7&Key modifier bit mask:\\
&5: shift, 6: alt, 7: ctrl\\
\hline
\end{longtable}
\end{center}
\vspace*{-14mm}
\subsection{Cycle Counter}
~\vspace*{-10mm}
\subsubsection{\texttt{CYC\$STATE}}
~\vspace*{-3mm}
\begin{center}
\begin{longtable}{|l|l|}
\hline
Bit&Description\\
\hline
\hline
0&Reset counter and start counting.\\
1&1: count, 0: inhibit\\
\hline
\end{longtable}
\end{center}
\vspace*{-14mm}
%
\subsection{EAE}
\subsection{\texttt{IO\$EAE\_CSR}}
\begin{center}
\begin{longtable}{|l|l|}
\hline
Bit&Description\\
\hline
\hline
0/1&Operation (MULU, MULS, DIVU, DIVS)\\
15&Busy if set\\
\hline
\end{longtable}
\end{center}
%
~\vspace*{-20mm}
\subsection{UART}
\subsubsection{\texttt{IO\$UART\_SRA}}
\begin{center}
\begin{longtable}{|l|l|}
\hline
Bit&Description\\
\hline
\hline
0&Character received.\\
1&Transmitter ready for next character.\\
\hline
\end{longtable}
\end{center}
\vspace*{-16mm}
%
\section{Code Examples}
\subsection{Typical Subroutine Call}
\begin{verbatim}
MOVE ..., R8 ; Setup parameters
...
RSUB SUBR, 1 ; Call subroutine
...
SUBR: ADD 0x0100, R14 ; Get free reg. set
...
SUB 0x0100, R14 ; Restore reg. set
MOVE @R13++, R15 ; RET
\end{verbatim}
\vspace*{-5mm}
\subsection{Compute $\sum_{i=0}^{16}{\texttt{0x0010}}$}
\begin{verbatim}
.ORG 0x8000
XOR R0, R0 ; Clear R0
MOVE 0x0010, R1 ; Upper limit
LOOP: ADD R1, R0 ; One summation
SUB 0x0001, R1 ; Decrement i
ABRA LOOP, !Z ; Loop if not zero
HALT
\end{verbatim}
\end{document}
a05beb9ceThis file is pinned to the selected release. Download the original to open it in your design tool.