pcb

v 20130925 2
C 43000 45000 1 0 0 header10-2.sym
{
T 43000 47000 5 10 0 1 0 0 1
device=HEADER10
T 43600 47100 5 10 1 1 0 0 1
refdes=J1
T 43000 45000 5 10 0 1 0 0 1
footprint=HEADER10_2
}
C 42700 46800 1 0 0 vcc.sym
{
T 42700 48500 5 8 0 0 0 0 1
footprint=none
T 42700 48300 5 8 0 0 0 0 1
symversion=1.0
T 42700 46800 5 10 0 0 0 0 1
net=3V3:1
T 42400 46800 5 10 1 1 0 0 1
value=3V3
}
N 42800 46800 43000 46800 4
C 44800 46700 1 90 0 agnd.sym
N 44600 46800 44400 46800 4
C 44600 46100 1 180 1 io-1.sym
{
T 45500 45900 5 10 0 0 180 6 1
net=I2C_SDA:1
T 44800 45500 5 10 0 0 180 6 1
device=none
T 45400 46000 5 10 1 1 180 7 1
value=I2C_SDA
}
N 44600 46000 44400 46000 4
C 42800 45900 1 0 1 output-1.sym
{
T 42700 46200 5 10 0 0 0 6 1
device=OUTPUT
T 42800 45900 5 10 0 0 0 6 1
net=I2C_SCL:1
T 42000 45900 5 10 1 1 0 6 1
value=I2C_SCL
}
N 42800 46000 43000 46000 4
C 48800 44700 1 0 0 24LCXXX.sym
{
T 51000 47100 5 10 0 0 0 0 1
footprint=SO8
T 51000 47500 5 10 0 0 0 0 1
device=24LC16B
T 50100 46000 5 10 1 1 0 3 1
refdes=U1
}
C 48600 45500 1 180 0 io-1.sym
{
T 47700 45300 5 10 0 0 180 0 1
net=I2C_SDA:1
T 48400 44900 5 10 0 0 180 0 1
device=none
T 47800 45400 5 10 1 1 180 1 1
value=I2C_SDA
}
N 48600 45400 48800 45400 4
C 48400 46100 1 270 1 agnd.sym
N 48600 46200 48800 46200 4
C 47800 45900 1 180 1 input-1.sym
{
T 47800 45600 5 10 0 0 180 6 1
device=INPUT
T 47800 45900 5 10 0 0 180 6 1
net=I2C_SCL:1
T 47700 45700 5 10 1 1 0 6 1
value=I2C_SCL
}
N 48600 45800 48800 45800 4
C 48500 46800 1 0 0 vcc.sym
{
T 48500 48500 5 8 0 0 0 0 1
footprint=none
T 48500 48300 5 8 0 0 0 0 1
symversion=1.0
T 48500 46800 5 10 0 0 0 0 1
net=3V3:1
T 48200 46800 5 10 1 1 0 0 1
value=3V3
}
N 48400 46600 48800 46600 4
C 51700 45500 1 90 1 agnd.sym
N 51500 45400 51300 45400 4
C 52600 46800 1 90 0 resistor-2.sym
{
T 52250 47200 5 10 0 0 90 0 1
device=RESISTOR
T 52400 47400 5 10 1 1 180 0 1
refdes=R1
T 52200 47000 5 10 1 1 0 0 1
value=0
T 52600 46800 5 10 0 1 0 0 1
footprint=0603
}
C 53200 46800 1 90 0 resistor-2.sym
{
T 52850 47200 5 10 0 0 90 0 1
device=RESISTOR
T 53000 47400 5 10 1 1 180 0 1
refdes=R2
T 52800 47000 5 10 1 1 0 0 1
value=0
T 53200 46800 5 10 0 1 0 0 1
footprint=0603
}
C 53800 46800 1 90 0 resistor-2.sym
{
T 53450 47200 5 10 0 0 90 0 1
device=RESISTOR
T 53600 47400 5 10 1 1 180 0 1
refdes=R3
T 53400 47000 5 10 1 1 0 0 1
value=0
T 53800 46800 5 10 0 1 0 0 1
footprint=0603
}
N 52500 47700 52500 48000 4
N 52500 48000 53700 48000 4
N 53700 48000 53700 47700 4
N 53100 47700 53100 48000 4
C 53000 48000 1 0 0 vcc.sym
{
T 53000 49700 5 8 0 0 0 0 1
footprint=none
T 53000 49500 5 8 0 0 0 0 1
symversion=1.0
T 53000 48000 5 10 0 0 0 0 1
net=3V3:1
T 52700 48000 5 10 1 1 0 0 1
value=3V3
}
C 52600 44600 1 90 0 resistor-2.sym
{
T 52250 45000 5 10 0 0 90 0 1
device=RESISTOR
T 52400 45200 5 10 1 1 180 0 1
refdes=R4
T 52100 44800 5 10 1 1 0 0 1
value=DNI
T 52600 44600 5 10 0 1 0 0 1
footprint=0603
}
C 53200 44600 1 90 0 resistor-2.sym
{
T 52850 45000 5 10 0 0 90 0 1
device=RESISTOR
T 53000 45200 5 10 1 1 180 0 1
refdes=R5
T 52700 44800 5 10 1 1 0 0 1
value=DNI
T 53200 44600 5 10 0 1 0 0 1
footprint=0603
}
C 53800 44600 1 90 0 resistor-2.sym
{
T 53450 45000 5 10 0 0 90 0 1
device=RESISTOR
T 53600 45200 5 10 1 1 180 0 1
refdes=R6
T 53300 44800 5 10 1 1 0 0 1
value=DNI
T 53800 44600 5 10 0 1 0 0 1
footprint=0603
}
N 52500 44600 52500 44300 4
N 52500 44300 53700 44300 4
N 53700 44300 53700 44600 4
N 53100 44600 53100 44300 4
C 53200 44100 1 0 1 agnd.sym
N 51300 46600 52500 46600 4
N 52500 45500 52500 46800 4
N 51300 46200 53100 46200 4
N 53100 45500 53100 46800 4
N 51300 45800 53700 45800 4
N 53700 45500 53700 46800 4
C 47500 46400 1 0 0 capacitor-1.sym
{
T 47700 47100 5 10 0 0 0 0 1
device=CAPACITOR
T 47600 46700 5 10 1 1 0 0 1
refdes=C1
T 47700 47300 5 10 0 0 0 0 1
symversion=0.1
T 47500 46400 5 10 1 1 0 0 1
value=0.1u
T 47500 46400 5 10 0 1 0 0 1
footprint=0603
}
N 48600 46800 48600 46600 4
C 47000 46500 1 270 1 agnd.sym
N 47200 46600 47500 46600 4