pcb

v 20121123 2
C 35000 40600 1 0 0 AD5620.sym
{
T 36800 42800 5 10 1 1 0 6 1
refdes=U3
T 35400 43000 5 10 0 0 0 0 1
device=AD5620BRJZ
T 35400 43200 5 10 0 0 0 0 1
footprint=SO8
}
C 38900 47400 1 0 1 header4-2.sym
{
T 38900 47400 5 10 0 1 0 0 1
footprint=KXOV97
T 38900 47400 5 10 0 1 0 0 1
device=KXOV97
T 38600 48300 5 10 1 1 0 6 1
refdes=KXOV97
}
C 36900 47400 1 90 0 capacitor-1.sym
{
T 36200 47600 5 10 0 0 90 0 1
device=CAPACITOR
T 36000 47600 5 10 0 0 90 0 1
symversion=0.1
T 36900 47400 5 10 0 1 0 0 1
footprint=0603
T 36500 48100 5 10 1 1 180 0 1
refdes=C3
T 36200 47600 5 10 1 1 0 0 1
value=0.01u
}
N 37500 48000 37200 48000 4
N 37200 48000 37200 48300 4
N 36000 48300 37200 48300 4
N 35800 47400 37200 47400 4
N 37200 47400 37200 47600 4
N 37200 47600 37500 47600 4
C 35700 47400 1 0 0 vcc.sym
{
T 35700 49100 5 8 0 0 0 0 1
footprint=none
T 35700 48900 5 8 0 0 0 0 1
symversion=1.0
T 35700 47400 5 10 0 0 0 0 1
net=3V3:1
T 35400 47400 5 10 1 1 0 0 1
value=3V3
}
N 38900 47600 39100 47600 4
C 39100 47500 1 0 0 output-1.sym
{
T 39200 47800 5 10 0 0 0 0 1
device=OUTPUT
T 39100 47500 5 10 0 0 0 0 1
net=MCLK:1
T 39900 47500 5 10 1 1 0 0 1
value=MCLK
}
C 43800 46300 1 0 0 input-1.sym
{
T 43800 46600 5 10 0 0 0 0 1
device=INPUT
T 43800 46300 5 10 0 0 0 0 1
net=MCLK:1
T 43200 46300 5 10 1 1 0 0 1
value=MCLK
}
N 44600 46400 44800 46400 4
C 49900 44000 1 0 0 vcc.sym
{
T 49900 45700 5 8 0 0 0 0 1
footprint=none
T 49900 45500 5 8 0 0 0 0 1
symversion=1.0
T 49900 44000 5 10 0 0 0 0 1
net=3V3:1
T 50000 44000 5 10 1 1 0 0 1
value=3V3
}
C 48300 43400 1 0 0 fb.sym
{
T 48700 43300 5 10 1 1 0 4 1
refdes=FB1
T 48300 45100 5 10 0 1 0 0 1
device=HI1206N101R-10
T 48300 43400 5 10 0 1 0 0 1
footprint=1206
}
C 49400 44000 1 270 0 capacitor-1.sym
{
T 50100 43800 5 10 0 0 270 0 1
device=CAPACITOR
T 50300 43800 5 10 0 0 270 0 1
symversion=0.1
T 49400 44000 5 10 0 1 180 0 1
footprint=0603
T 49700 43700 5 10 1 1 0 0 1
refdes=C10
T 49700 43300 5 10 1 1 0 0 1
value=0.1u
}
N 50000 44000 47000 44000 4
C 47800 43600 1 270 0 capacitor-1.sym
{
T 48500 43400 5 10 0 0 270 0 1
device=CAPACITOR
T 48700 43400 5 10 0 0 270 0 1
symversion=0.1
T 47800 43600 5 10 0 1 180 0 1
footprint=0603
T 48100 43300 5 10 1 1 0 0 1
refdes=C8
T 48100 42900 5 10 1 1 0 0 1
value=0.1u
}
N 47000 43600 48300 43600 4
C 43800 45900 1 0 0 input-1.sym
{
T 43800 46200 5 10 0 0 0 0 1
device=INPUT
T 43800 45900 5 10 0 0 0 0 1
net=RESET:1
T 43100 45900 5 10 1 1 0 0 1
value=RESET
}
N 44600 46000 44800 46000 4
N 47000 42800 47400 42800 4
N 47400 42700 47400 43200 4
C 43800 45500 1 0 0 input-1.sym
{
T 43800 45800 5 10 0 0 0 0 1
device=INPUT
T 43800 45500 5 10 0 0 0 0 1
net=SDATA:1
T 43100 45500 5 10 1 1 0 0 1
value=SDATA
}
N 44600 45600 44800 45600 4
C 43800 45100 1 0 0 input-1.sym
{
T 43800 45400 5 10 0 0 0 0 1
device=INPUT
T 43800 45100 5 10 0 0 0 0 1
net=SCLK:1
T 43200 45100 5 10 1 1 0 0 1
value=SCLK
}
N 44600 45200 44800 45200 4
C 43800 44700 1 0 0 input-1.sym
{
T 43800 45000 5 10 0 0 0 0 1
device=INPUT
T 43800 44700 5 10 0 0 0 0 1
net=CS1:1
T 43300 44700 5 10 1 1 0 0 1
value=CS1
}
N 44600 44800 44800 44800 4
C 48300 45400 1 180 0 capacitor-1.sym
{
T 48100 44700 5 10 0 1 180 0 1
device=CAPACITOR
T 48300 45400 5 10 0 1 270 0 1
footprint=0603
T 47400 45000 5 10 1 1 0 0 1
refdes=C6
T 48000 45000 5 10 1 1 0 0 1
value=0.01u
}
C 48500 45200 1 0 0 vcc.sym
{
T 48500 46900 5 8 0 0 0 0 1
footprint=none
T 48500 46700 5 8 0 0 0 0 1
symversion=1.0
T 48500 45200 5 10 0 0 0 0 1
net=3V3:1
T 48600 45200 5 10 1 1 0 0 1
value=3V3
}
C 43700 43900 1 0 0 resistor-2.sym
{
T 44100 44250 5 10 0 1 0 0 1
device=RESISTOR
T 43700 43900 5 10 0 1 0 0 1
footprint=0603
T 43800 44100 5 10 1 1 0 0 1
refdes=R2
T 44200 44100 5 10 1 1 0 0 1
value=6.8k
}
N 44600 44000 44800 44000 4
N 42800 44000 43700 44000 4
N 47000 46400 52700 46400 4
N 47000 46000 52700 46000 4
N 47400 45200 47000 45200 4
N 48600 45200 48300 45200 4
C 48100 45000 1 180 0 capacitor-1.sym
{
T 47900 44300 5 10 0 1 180 0 1
device=CAPACITOR
T 48100 45000 5 10 0 1 270 0 1
footprint=0603
T 47200 44600 5 10 1 1 0 0 1
refdes=C7
T 47800 44600 5 10 1 1 0 0 1
value=0.1u
}
N 47200 44800 47000 44800 4
N 48300 44800 48100 44800 4
C 43700 44300 1 0 0 resistor-2.sym
{
T 44100 44650 5 10 0 1 0 0 1
device=RESISTOR
T 43700 44300 5 10 0 1 0 0 1
footprint=0603
T 43800 44500 5 10 1 1 0 0 1
refdes=R3
T 44300 44500 5 10 1 1 0 0 1
value=0
}
N 44600 44400 44800 44400 4
N 43500 44400 43700 44400 4
N 47000 43200 47400 43200 4
C 48100 45800 1 180 0 capacitor-1.sym
{
T 47900 45100 5 10 0 1 180 0 1
device=CAPACITOR
T 48100 45800 5 10 0 1 270 0 1
footprint=0603
T 47200 45400 5 10 1 1 0 0 1
refdes=C5
T 47800 45400 5 10 1 1 0 0 1
value=0.1u
}
N 47200 45600 47000 45600 4
N 48300 45600 48100 45600 4
C 34100 42200 1 0 0 input-1.sym
{
T 34100 42500 5 10 0 0 0 0 1
device=INPUT
T 34100 42200 5 10 0 0 0 0 1
net=CS3:1
T 33600 42200 5 10 1 1 0 0 1
value=CS3
}
N 34900 42300 35100 42300 4
C 34100 41800 1 0 0 input-1.sym
{
T 34100 42100 5 10 0 0 0 0 1
device=INPUT
T 34100 41800 5 10 0 0 0 0 1
net=SDATA:1
T 33400 41800 5 10 1 1 0 0 1
value=SDATA
}
N 34900 41900 35100 41900 4
C 34100 41400 1 0 0 input-1.sym
{
T 34100 41700 5 10 0 0 0 0 1
device=INPUT
T 34100 41400 5 10 0 0 0 0 1
net=SCLK:1
T 33500 41400 5 10 1 1 0 0 1
value=SCLK
}
N 34900 41500 35100 41500 4
N 37100 42300 39600 42300 4
N 37300 41900 37100 41900 4
C 37800 41500 1 0 0 vcc.sym
{
T 37800 43200 5 8 0 0 0 0 1
footprint=none
T 37800 43000 5 8 0 0 0 0 1
symversion=1.0
T 37800 41500 5 10 0 0 0 0 1
net=3V3:1
T 37900 41500 5 10 1 1 0 0 1
value=3V3
}
N 37900 41500 37100 41500 4
N 37300 41100 37100 41100 4
N 37300 41900 37300 42300 4
C 34000 40900 1 0 0 capacitor-1.sym
{
T 34200 41600 5 10 0 1 0 0 1
device=CAPACITOR
T 34000 40900 5 10 0 1 90 0 1
footprint=0603
T 34300 41000 5 10 1 1 180 0 1
refdes=C9
T 34900 41000 5 10 1 1 180 0 1
value=0.1u
}
N 34900 41100 35100 41100 4
N 33800 41100 34000 41100 4
C 52400 45600 1 0 0 vcc.sym
{
T 52400 47300 5 8 0 0 0 0 1
footprint=none
T 52400 47100 5 8 0 0 0 0 1
symversion=1.0
T 52400 45600 5 10 0 0 0 0 1
net=3V3:1
T 52100 45600 5 10 1 1 0 0 1
value=3V3
}
N 52500 45600 52700 45600 4
C 53200 44400 1 180 1 resistor-2.sym
{
T 53600 44050 5 10 0 1 180 6 1
device=RESISTOR
T 53200 44400 5 10 0 1 90 2 1
footprint=0603
T 54000 44400 5 10 1 1 0 6 1
refdes=R6
T 53500 44400 5 10 1 1 0 6 1
value=1k
}
C 52200 43400 1 90 0 capacitor-1.sym
{
T 51500 43600 5 10 0 1 270 8 1
device=CAPACITOR
T 52200 43400 5 10 0 1 0 6 1
footprint=0603
T 52400 44100 5 10 1 1 180 0 1
refdes=C12
T 52400 43700 5 10 1 1 180 0 1
value=0.1u
}
C 52700 43400 1 90 0 capacitor-1.sym
{
T 52000 43600 5 10 0 1 270 8 1
device=CAPACITOR
T 52700 43400 5 10 0 1 0 6 1
footprint=0603
T 52900 44100 5 10 1 1 180 0 1
refdes=C11
T 52900 43700 5 10 1 1 180 0 1
value=10u
}
C 54200 44300 1 0 1 vcc.sym
{
T 54200 46000 5 8 0 0 0 6 1
footprint=none
T 54200 45800 5 8 0 0 0 6 1
symversion=1.0
T 54200 44300 5 10 0 0 0 6 1
net=3V3:1
T 54500 44300 5 10 1 1 0 6 1
value=3V3
}
C 52900 43400 1 270 1 resistor-2.sym
{
T 53250 43800 5 10 0 1 90 2 1
device=RESISTOR
T 52900 43400 5 10 0 1 0 6 1
footprint=0603
T 53400 43900 5 10 1 1 0 6 1
refdes=R7
T 53400 43600 5 10 1 1 0 6 1
value=1k
}
N 52000 44300 53200 44300 4
N 52000 43400 53000 43400 4
C 56600 46200 1 0 1 con_SMA.sym
{
T 56600 46200 5 10 0 1 0 6 1
footprint=sma_jack
T 56600 46200 5 10 0 1 0 6 1
device=SMA
T 56600 46550 5 10 1 1 0 6 1
refdes=SMA1
}
N 56500 46100 56500 46200 4
C 56100 45600 1 0 1 vcc.sym
{
T 56100 47300 5 8 0 0 0 6 1
footprint=none
T 56100 47100 5 8 0 0 0 6 1
symversion=1.0
T 56100 45600 5 10 0 0 0 6 1
net=3V3:1
T 56400 45600 5 10 1 1 0 6 1
value=3V3
}
N 56000 45600 54700 45600 4
N 54900 45200 54700 45200 4
C 56400 45800 1 0 0 agnd.sym
C 54800 44900 1 0 0 agnd.sym
C 52600 43100 1 0 1 agnd.sym
C 37200 40600 1 0 0 agnd.sym
C 33500 41200 1 270 0 agnd.sym
C 47300 42400 1 0 0 agnd.sym
C 47900 42400 1 0 0 agnd.sym
C 49500 42800 1 0 0 agnd.sym
C 48600 45500 1 90 0 agnd.sym
C 48600 44700 1 90 0 agnd.sym
C 43200 44500 1 270 0 agnd.sym
C 35700 48400 1 270 0 agnd.sym
C 49800 45000 1 90 0 resistor-2.sym
{
T 49450 45400 5 10 0 1 90 0 1
device=RESISTOR
T 49800 45000 5 10 0 1 0 0 1
footprint=0603
T 49300 45500 5 10 1 1 0 0 1
refdes=R4
T 49300 45200 5 10 1 1 0 0 1
value=200
}
C 50400 45000 1 90 0 resistor-2.sym
{
T 50050 45400 5 10 0 1 90 0 1
device=RESISTOR
T 50400 45000 5 10 0 1 0 0 1
footprint=0603
T 49900 45500 5 10 1 1 0 0 1
refdes=R5
T 49900 45200 5 10 1 1 0 0 1
value=200
}
C 49900 44700 1 0 0 agnd.sym
N 49700 45000 50300 45000 4
N 49700 45900 49700 46400 4
N 50300 45900 50300 46000 4
C 36200 39800 1 0 0 output-1.sym
{
T 36300 40100 5 10 0 0 0 0 1
device=OUTPUT
T 36200 39800 5 10 0 0 0 0 1
net=SCLK:1
T 37000 39800 5 10 1 1 0 0 1
value=SCLK
}
N 36200 39900 36000 39900 4
C 36200 39400 1 0 0 output-1.sym
{
T 36300 39700 5 10 0 0 0 0 1
device=OUTPUT
T 36200 39400 5 10 0 0 0 0 1
net=SDATA:1
T 37000 39400 5 10 1 1 0 0 1
value=SDATA
}
N 36200 39500 36000 39500 4
C 36200 39000 1 0 0 output-1.sym
{
T 36300 39300 5 10 0 0 0 0 1
device=OUTPUT
T 36200 39000 5 10 0 0 0 0 1
net=CS1:1
T 37000 39000 5 10 1 1 0 0 1
value=CS1
}
N 36200 39100 36000 39100 4
C 36200 38600 1 0 0 output-1.sym
{
T 36300 38900 5 10 0 0 0 0 1
device=OUTPUT
T 36200 38600 5 10 0 0 0 0 1
net=CS2:1
T 37000 38600 5 10 1 1 0 0 1
value=CS2
}
N 36200 38700 36000 38700 4
C 36200 37800 1 0 0 output-1.sym
{
T 36300 38100 5 10 0 0 0 0 1
device=OUTPUT
T 36200 37800 5 10 0 0 0 0 1
net=RESET:1
T 37000 37800 5 10 1 1 0 0 1
value=RESET
}
C 52600 44700 1 0 0 AD8130.sym
{
T 54400 46900 5 10 1 1 0 6 1
refdes=U4
T 53000 47100 5 10 0 0 0 0 1
device=AD8130ARZ
T 53000 47300 5 10 0 0 0 0 1
footprint=SO8
}
N 54700 46000 54900 46000 4
N 54900 46000 54900 46400 4
C 56000 46500 1 180 0 resistor-2.sym
{
T 55600 46150 5 10 0 1 180 0 1
device=RESISTOR
T 56000 46500 5 10 0 1 90 0 1
footprint=0603
T 55200 46500 5 10 1 1 0 0 1
refdes=R8
T 55700 46500 5 10 1 1 0 0 1
value=10
}
N 54700 46400 55100 46400 4
N 56000 46400 56150 46400 4
C 55600 44700 1 270 1 capacitor-1.sym
{
T 56300 44900 5 10 0 1 270 6 1
device=CAPACITOR
T 55600 44700 5 10 0 1 0 0 1
footprint=0603
T 55800 45400 5 10 1 1 180 6 1
refdes=C14
T 55800 45000 5 10 1 1 180 6 1
value=10u
}
C 55000 44700 1 270 1 capacitor-1.sym
{
T 55700 44900 5 10 0 1 270 6 1
device=CAPACITOR
T 55000 44700 5 10 0 1 0 0 1
footprint=0603
T 55200 45400 5 10 1 1 180 6 1
refdes=C13
T 55200 45000 5 10 1 1 180 6 1
value=0.1u
}
C 55400 44400 1 0 0 agnd.sym
N 55800 44700 55200 44700 4
C 44700 42300 1 0 0 AD9834.sym
{
T 46700 46900 5 10 1 1 0 6 1
refdes=U2
T 45100 47100 5 10 0 0 0 0 1
device=AD9834BRUZ
T 45100 47300 5 10 0 0 0 0 1
footprint=TSSOP20
}
C 39500 40600 1 0 0 AD8666.sym
{
T 41300 42800 5 10 1 1 0 6 1
refdes=U5
T 39900 43000 5 10 0 0 0 0 1
device=AD8666ARMZ
T 39900 43200 5 10 0 0 0 0 1
footprint=MSOP8
}
N 42800 42300 41600 42300 4
N 41800 42300 41800 43200 4
N 41800 43200 39400 43200 4
N 39400 41900 39400 43200 4
N 39400 41900 39600 41900 4
N 38900 42300 38900 41500 4
N 38900 41500 39600 41500 4
C 42000 41500 1 270 0 capacitor-1.sym
{
T 42700 41300 5 10 0 0 270 0 1
device=CAPACITOR
T 42900 41300 5 10 0 0 270 0 1
symversion=0.1
T 42000 41500 5 10 0 1 180 0 1
footprint=0603
T 42600 41300 5 10 1 1 180 0 1
refdes=C15
T 42600 40900 5 10 1 1 180 0 1
value=0.1u
}
N 41600 41500 42400 41500 4
C 42100 40300 1 0 0 agnd.sym
N 41800 41100 41600 41100 4
C 41700 40600 1 0 0 agnd.sym
N 41800 40900 41800 41100 4
C 42300 41500 1 0 0 vcc.sym
{
T 42300 43200 5 8 0 0 0 0 1
footprint=none
T 42300 43000 5 8 0 0 0 0 1
symversion=1.0
T 42300 41500 5 10 0 0 0 0 1
net=3V3:1
T 42400 41500 5 10 1 1 0 0 1
value=3V3
}
C 50700 45900 1 270 0 capacitor-1.sym
{
T 51400 45700 5 10 0 0 270 0 1
device=CAPACITOR
T 51600 45700 5 10 0 0 270 0 1
symversion=0.1
T 50700 45900 5 10 0 1 180 0 1
footprint=0603
T 50500 45500 5 10 1 1 0 0 1
refdes=C16
T 50600 45200 5 10 1 1 0 0 1
value=20p
}
C 51300 45900 1 270 0 capacitor-1.sym
{
T 52000 45700 5 10 0 0 270 0 1
device=CAPACITOR
T 52200 45700 5 10 0 0 270 0 1
symversion=0.1
T 51300 45900 5 10 0 1 180 0 1
footprint=0603
T 51100 45500 5 10 1 1 0 0 1
refdes=C17
T 51200 45200 5 10 1 1 0 0 1
value=20p
}
N 50900 45900 50900 46400 4
N 51500 45900 51500 46000 4
N 50900 45000 51500 45000 4
C 51100 44700 1 0 0 agnd.sym
N 41600 41900 42800 41900 4
N 39600 41100 39400 41100 4
N 39400 41100 39400 40100 4
N 39400 40100 42800 40100 4
N 42800 37900 42800 41900 4
N 42800 42300 42800 44000 4
N 52500 44300 52500 45200 4
N 52500 45200 52700 45200 4
C 43800 43500 1 0 0 input-1.sym
{
T 43800 43800 5 10 0 0 0 0 1
device=INPUT
T 43800 43500 5 10 0 0 0 0 1
net=FSELECT:1
T 42900 43500 5 10 1 1 0 0 1
value=FSELECT
}
N 44600 43600 44800 43600 4
C 43800 43100 1 0 0 input-1.sym
{
T 43800 43400 5 10 0 0 0 0 1
device=INPUT
T 43800 43100 5 10 0 0 0 0 1
net=PSELECT:1
T 42900 43100 5 10 1 1 0 0 1
value=PSELECT
}
N 44600 43200 44800 43200 4
C 43800 42700 1 0 0 input-1.sym
{
T 43800 43000 5 10 0 0 0 0 1
device=INPUT
T 43800 42700 5 10 0 0 0 0 1
net=SLEEP:1
T 43100 42700 5 10 1 1 0 0 1
value=SLEEP
}
N 44600 42800 44800 42800 4
C 43800 40200 1 0 0 input-1.sym
{
T 43800 40500 5 10 0 0 0 0 1
device=INPUT
T 43800 40200 5 10 0 0 0 0 1
net=MCLK:1
T 43200 40200 5 10 1 1 0 0 1
value=MCLK
}
N 44600 40300 44800 40300 4
C 49900 37900 1 0 0 vcc.sym
{
T 49900 39600 5 8 0 0 0 0 1
footprint=none
T 49900 39400 5 8 0 0 0 0 1
symversion=1.0
T 49900 37900 5 10 0 0 0 0 1
net=3V3:1
T 50000 37900 5 10 1 1 0 0 1
value=3V3
}
C 48300 37300 1 0 0 fb.sym
{
T 48300 39000 5 10 0 1 0 0 1
device=HI1206N101R-10
T 48300 37300 5 10 0 1 0 0 1
footprint=1206
T 48700 37200 5 10 1 1 0 4 1
refdes=FB2
}
C 49400 37900 1 270 0 capacitor-1.sym
{
T 50100 37700 5 10 0 0 270 0 1
device=CAPACITOR
T 50300 37700 5 10 0 0 270 0 1
symversion=0.1
T 49400 37900 5 10 0 1 180 0 1
footprint=0603
T 49700 37600 5 10 1 1 0 0 1
refdes=C18
T 49700 37200 5 10 1 1 0 0 1
value=0.1u
}
N 50000 37900 47000 37900 4
C 47800 37500 1 270 0 capacitor-1.sym
{
T 48500 37300 5 10 0 0 270 0 1
device=CAPACITOR
T 48700 37300 5 10 0 0 270 0 1
symversion=0.1
T 47800 37500 5 10 0 1 180 0 1
footprint=0603
T 48100 37200 5 10 1 1 0 0 1
refdes=C19
T 48100 36800 5 10 1 1 0 0 1
value=0.1u
}
N 47000 37500 48300 37500 4
C 43800 39800 1 0 0 input-1.sym
{
T 43800 40100 5 10 0 0 0 0 1
device=INPUT
T 43800 39800 5 10 0 0 0 0 1
net=RESET:1
T 43100 39800 5 10 1 1 0 0 1
value=RESET
}
N 44600 39900 44800 39900 4
N 47000 36700 47400 36700 4
N 47400 36600 47400 37100 4
C 43800 39400 1 0 0 input-1.sym
{
T 43800 39700 5 10 0 0 0 0 1
device=INPUT
T 43800 39400 5 10 0 0 0 0 1
net=SDATA:1
T 43100 39400 5 10 1 1 0 0 1
value=SDATA
}
N 44600 39500 44800 39500 4
C 43800 39000 1 0 0 input-1.sym
{
T 43800 39300 5 10 0 0 0 0 1
device=INPUT
T 43800 39000 5 10 0 0 0 0 1
net=SCLK:1
T 43200 39000 5 10 1 1 0 0 1
value=SCLK
}
N 44600 39100 44800 39100 4
N 44600 38700 44800 38700 4
C 48300 39300 1 180 0 capacitor-1.sym
{
T 48100 38600 5 10 0 1 180 0 1
device=CAPACITOR
T 48300 39300 5 10 0 1 270 0 1
footprint=0603
T 47400 38900 5 10 1 1 0 0 1
refdes=C20
T 48000 38900 5 10 1 1 0 0 1
value=0.01u
}
C 48500 39100 1 0 0 vcc.sym
{
T 48500 40800 5 8 0 0 0 0 1
footprint=none
T 48500 40600 5 8 0 0 0 0 1
symversion=1.0
T 48500 39100 5 10 0 0 0 0 1
net=3V3:1
T 48600 39100 5 10 1 1 0 0 1
value=3V3
}
C 43700 37800 1 0 0 resistor-2.sym
{
T 44100 38150 5 10 0 1 0 0 1
device=RESISTOR
T 43700 37800 5 10 0 1 0 0 1
footprint=0603
T 43800 38000 5 10 1 1 0 0 1
refdes=R9
T 44200 38000 5 10 1 1 0 0 1
value=6.8k
}
N 44600 37900 44800 37900 4
N 47000 40300 52700 40300 4
N 47000 39900 52700 39900 4
N 47400 39100 47000 39100 4
N 48600 39100 48300 39100 4
C 48100 38900 1 180 0 capacitor-1.sym
{
T 47900 38200 5 10 0 1 180 0 1
device=CAPACITOR
T 48100 38900 5 10 0 1 270 0 1
footprint=0603
T 47200 38500 5 10 1 1 0 0 1
refdes=C21
T 47800 38500 5 10 1 1 0 0 1
value=0.1u
}
N 47200 38700 47000 38700 4
N 48300 38700 48100 38700 4
C 43700 38200 1 0 0 resistor-2.sym
{
T 44100 38550 5 10 0 1 0 0 1
device=RESISTOR
T 43700 38200 5 10 0 1 0 0 1
footprint=0603
T 43800 38400 5 10 1 1 0 0 1
refdes=R10
T 44300 38400 5 10 1 1 0 0 1
value=0
}
N 44600 38300 44800 38300 4
N 43500 38300 43700 38300 4
N 47000 37100 47400 37100 4
C 48100 39700 1 180 0 capacitor-1.sym
{
T 47900 39000 5 10 0 1 180 0 1
device=CAPACITOR
T 48100 39700 5 10 0 1 270 0 1
footprint=0603
T 47200 39300 5 10 1 1 0 0 1
refdes=C22
T 47800 39300 5 10 1 1 0 0 1
value=0.1u
}
N 47200 39500 47000 39500 4
N 48300 39500 48100 39500 4
C 52400 39500 1 0 0 vcc.sym
{
T 52400 41200 5 8 0 0 0 0 1
footprint=none
T 52400 41000 5 8 0 0 0 0 1
symversion=1.0
T 52400 39500 5 10 0 0 0 0 1
net=3V3:1
T 52100 39500 5 10 1 1 0 0 1
value=3V3
}
N 52500 39500 52700 39500 4
C 53200 38300 1 180 1 resistor-2.sym
{
T 53600 37950 5 10 0 1 180 6 1
device=RESISTOR
T 53200 38300 5 10 0 1 90 2 1
footprint=0603
T 54000 38300 5 10 1 1 0 6 1
refdes=R11
T 53500 38300 5 10 1 1 0 6 1
value=1k
}
C 52200 37300 1 90 0 capacitor-1.sym
{
T 51500 37500 5 10 0 1 270 8 1
device=CAPACITOR
T 52200 37300 5 10 0 1 0 6 1
footprint=0603
T 52400 38000 5 10 1 1 180 0 1
refdes=C23
T 52400 37600 5 10 1 1 180 0 1
value=0.1u
}
C 52700 37300 1 90 0 capacitor-1.sym
{
T 52000 37500 5 10 0 1 270 8 1
device=CAPACITOR
T 52700 37300 5 10 0 1 0 6 1
footprint=0603
T 52900 38000 5 10 1 1 180 0 1
refdes=C24
T 52900 37600 5 10 1 1 180 0 1
value=10u
}
C 54200 38200 1 0 1 vcc.sym
{
T 54200 39900 5 8 0 0 0 6 1
footprint=none
T 54200 39700 5 8 0 0 0 6 1
symversion=1.0
T 54200 38200 5 10 0 0 0 6 1
net=3V3:1
T 54500 38200 5 10 1 1 0 6 1
value=3V3
}
C 52900 37300 1 270 1 resistor-2.sym
{
T 53250 37700 5 10 0 1 90 2 1
device=RESISTOR
T 52900 37300 5 10 0 1 0 6 1
footprint=0603
T 53400 37800 5 10 1 1 0 6 1
refdes=R12
T 53400 37500 5 10 1 1 0 6 1
value=1k
}
N 52000 38200 53200 38200 4
N 52000 37300 53000 37300 4
C 56600 40100 1 0 1 con_SMA.sym
{
T 56600 40100 5 10 0 1 0 6 1
footprint=sma_jack
T 56600 40100 5 10 0 1 0 6 1
device=SMA
T 56600 40450 5 10 1 1 0 6 1
refdes=SMA2
}
N 56500 40000 56500 40100 4
C 56100 39500 1 0 1 vcc.sym
{
T 56100 41200 5 8 0 0 0 6 1
footprint=none
T 56100 41000 5 8 0 0 0 6 1
symversion=1.0
T 56100 39500 5 10 0 0 0 6 1
net=3V3:1
T 56400 39500 5 10 1 1 0 6 1
value=3V3
}
N 56000 39500 54700 39500 4
N 54900 39100 54700 39100 4
C 56400 39700 1 0 0 agnd.sym
C 54800 38800 1 0 0 agnd.sym
C 52600 37000 1 0 1 agnd.sym
C 47300 36300 1 0 0 agnd.sym
C 47900 36300 1 0 0 agnd.sym
C 49500 36700 1 0 0 agnd.sym
C 48600 39400 1 90 0 agnd.sym
C 48600 38600 1 90 0 agnd.sym
C 43200 38400 1 270 0 agnd.sym
C 49800 38900 1 90 0 resistor-2.sym
{
T 49450 39300 5 10 0 1 90 0 1
device=RESISTOR
T 49800 38900 5 10 0 1 0 0 1
footprint=0603
T 49300 39400 5 10 1 1 0 0 1
refdes=R13
T 49300 39100 5 10 1 1 0 0 1
value=200
}
C 50400 38900 1 90 0 resistor-2.sym
{
T 50050 39300 5 10 0 1 90 0 1
device=RESISTOR
T 50400 38900 5 10 0 1 0 0 1
footprint=0603
T 49900 39400 5 10 1 1 0 0 1
refdes=R14
T 49900 39100 5 10 1 1 0 0 1
value=200
}
C 49900 38600 1 0 0 agnd.sym
N 49700 38900 50300 38900 4
N 49700 39800 49700 40300 4
N 50300 39800 50300 39900 4
C 52600 38600 1 0 0 AD8130.sym
{
T 53000 41000 5 10 0 0 0 0 1
device=AD8130ARZ
T 53000 41200 5 10 0 0 0 0 1
footprint=SO8
T 54400 40800 5 10 1 1 0 6 1
refdes=U6
}
N 54700 39900 54900 39900 4
N 54900 39900 54900 40300 4
C 56000 40400 1 180 0 resistor-2.sym
{
T 55600 40050 5 10 0 1 180 0 1
device=RESISTOR
T 56000 40400 5 10 0 1 90 0 1
footprint=0603
T 55200 40400 5 10 1 1 0 0 1
refdes=R15
T 55700 40400 5 10 1 1 0 0 1
value=10
}
N 54700 40300 55100 40300 4
N 56000 40300 56150 40300 4
C 55600 38600 1 270 1 capacitor-1.sym
{
T 56300 38800 5 10 0 1 270 6 1
device=CAPACITOR
T 55600 38600 5 10 0 1 0 0 1
footprint=0603
T 55800 39300 5 10 1 1 180 6 1
refdes=C25
T 55800 38900 5 10 1 1 180 6 1
value=10u
}
C 55000 38600 1 270 1 capacitor-1.sym
{
T 55700 38800 5 10 0 1 270 6 1
device=CAPACITOR
T 55000 38600 5 10 0 1 0 0 1
footprint=0603
T 55200 39300 5 10 1 1 180 6 1
refdes=C26
T 55200 38900 5 10 1 1 180 6 1
value=0.1u
}
C 55400 38300 1 0 0 agnd.sym
N 55800 38600 55200 38600 4
C 44700 36200 1 0 0 AD9834.sym
{
T 45100 41000 5 10 0 0 0 0 1
device=AD9834BRUZ
T 45100 41200 5 10 0 0 0 0 1
footprint=TSSOP20
T 46700 40800 5 10 1 1 0 6 1
refdes=U7
}
C 50700 39800 1 270 0 capacitor-1.sym
{
T 51400 39600 5 10 0 0 270 0 1
device=CAPACITOR
T 51600 39600 5 10 0 0 270 0 1
symversion=0.1
T 50700 39800 5 10 0 1 180 0 1
footprint=0603
T 50500 39400 5 10 1 1 0 0 1
refdes=C27
T 50600 39100 5 10 1 1 0 0 1
value=20p
}
C 51300 39800 1 270 0 capacitor-1.sym
{
T 52000 39600 5 10 0 0 270 0 1
device=CAPACITOR
T 52200 39600 5 10 0 0 270 0 1
symversion=0.1
T 51300 39800 5 10 0 1 180 0 1
footprint=0603
T 51100 39400 5 10 1 1 0 0 1
refdes=C28
T 51200 39100 5 10 1 1 0 0 1
value=20p
}
N 50900 39800 50900 40300 4
N 51500 39800 51500 39900 4
N 50900 38900 51500 38900 4
C 51100 38600 1 0 0 agnd.sym
N 52500 38200 52500 39100 4
N 52500 39100 52700 39100 4
C 43800 37400 1 0 0 input-1.sym
{
T 43800 37700 5 10 0 0 0 0 1
device=INPUT
T 43800 37400 5 10 0 0 0 0 1
net=FSELECT:1
T 42900 37400 5 10 1 1 0 0 1
value=FSELECT
}
N 44600 37500 44800 37500 4
C 43800 37000 1 0 0 input-1.sym
{
T 43800 37300 5 10 0 0 0 0 1
device=INPUT
T 43800 37000 5 10 0 0 0 0 1
net=PSELECT:1
T 42900 37000 5 10 1 1 0 0 1
value=PSELECT
}
N 44600 37100 44800 37100 4
C 43800 36600 1 0 0 input-1.sym
{
T 43800 36900 5 10 0 0 0 0 1
device=INPUT
T 43800 36600 5 10 0 0 0 0 1
net=SLEEP:1
T 43100 36600 5 10 1 1 0 0 1
value=SLEEP
}
N 44600 36700 44800 36700 4
N 42800 37900 43700 37900 4
C 43800 38600 1 0 0 input-1.sym
{
T 43800 38900 5 10 0 0 0 0 1
device=INPUT
T 43800 38600 5 10 0 0 0 0 1
net=CS2:1
T 43300 38600 5 10 1 1 0 0 1
value=CS2
}
C 36200 38200 1 0 0 output-1.sym
{
T 36300 38500 5 10 0 0 0 0 1
device=OUTPUT
T 36200 38200 5 10 0 0 0 0 1
net=CS3:1
T 37000 38200 5 10 1 1 0 0 1
value=CS3
}
N 36200 38300 36000 38300 4
N 36200 36300 36000 36300 4
C 36100 35800 1 0 0 agnd.sym
N 36200 36100 36200 36300 4
N 36200 37900 36000 37900 4
C 38000 37400 1 0 0 output-1.sym
{
T 38100 37700 5 10 0 0 0 0 1
device=OUTPUT
T 38000 37400 5 10 0 0 0 0 1
net=FSELECT:1
T 38800 37400 5 10 1 1 0 0 1
value=FSELECT
}
N 38000 37500 36000 37500 4
C 38000 37000 1 0 0 output-1.sym
{
T 38100 37300 5 10 0 0 0 0 1
device=OUTPUT
T 38000 37000 5 10 0 0 0 0 1
net=PSELECT:1
T 38800 37000 5 10 1 1 0 0 1
value=PSELECT
}
N 38000 37100 36000 37100 4
C 38000 36600 1 0 0 output-1.sym
{
T 38100 36900 5 10 0 0 0 0 1
device=OUTPUT
T 38000 36600 5 10 0 0 0 0 1
net=SLEEP:1
T 38800 36600 5 10 1 1 0 0 1
value=SLEEP
}
N 38000 36700 36000 36700 4
C 36500 35600 1 270 1 resistor-2.sym
{
T 36850 36000 5 10 0 1 90 2 1
device=RESISTOR
T 36500 35600 5 10 0 1 0 6 1
footprint=0603
T 36700 36200 5 10 1 1 180 6 1
refdes=R16
T 36700 36000 5 10 1 1 180 6 1
value=5k
}
C 37100 35600 1 270 1 resistor-2.sym
{
T 37450 36000 5 10 0 1 90 2 1
device=RESISTOR
T 37100 35600 5 10 0 1 0 6 1
footprint=0603
T 37300 36200 5 10 1 1 180 6 1
refdes=R17
T 37300 36000 5 10 1 1 180 6 1
value=5k
}
C 37700 35600 1 270 1 resistor-2.sym
{
T 38050 36000 5 10 0 1 90 2 1
device=RESISTOR
T 37700 35600 5 10 0 1 0 6 1
footprint=0603
T 38000 36200 5 10 1 1 180 6 1
refdes=R18
T 37900 36000 5 10 1 1 180 6 1
value=5k
}
C 37100 35300 1 0 0 agnd.sym
N 36600 37500 36600 36500 4
N 37200 37100 37200 36500 4
N 37800 36700 37800 36500 4
N 36600 35600 37800 35600 4
N 49100 37900 49100 37500 4
N 49100 43600 49100 44000 4
C 36000 36100 1 0 1 jumper10.sym
{
T 35000 37100 5 8 0 0 0 6 1
device=JUMPER10
T 35600 40200 5 10 1 1 0 6 1
refdes=J2
T 35000 36900 5 8 0 0 0 6 1
footprint=JUMPER10
}
C 37500 41500 1 270 0 capacitor-1.sym
{
T 38200 41300 5 10 0 0 270 0 1
device=CAPACITOR
T 38400 41300 5 10 0 0 270 0 1
symversion=0.1
T 37500 41500 5 10 0 1 180 0 1
footprint=0603
T 38100 41300 5 10 1 1 180 0 1
refdes=C29
T 38100 40900 5 10 1 1 180 0 1
value=0.1u
}
C 37600 40300 1 0 0 agnd.sym
N 37300 40900 37300 41100 4
C 38200 42300 1 270 0 capacitor-1.sym
{
T 38900 42100 5 10 0 0 270 0 1
device=CAPACITOR
T 39100 42100 5 10 0 0 270 0 1
symversion=0.1
T 38200 42300 5 10 0 1 180 0 1
footprint=0603
T 38800 42100 5 10 1 1 180 0 1
refdes=C30
T 38800 41700 5 10 1 1 180 0 1
value=0.1u
}
C 38300 41100 1 0 0 agnd.sym
C 36700 43900 1 0 0 ADP3335.sym
{
T 37100 46300 5 10 0 1 0 0 1
device=ADP3335
T 37100 46500 5 10 0 1 0 0 1
footprint=MSOP8
T 38500 46100 5 10 1 1 0 6 1
refdes=U1
}
N 36800 44400 36000 44400 4
N 36000 44300 36000 44500 4
N 38800 45600 41300 45600 4
N 39100 44800 39100 45600 4
N 39100 45200 38800 45200 4
N 39100 44800 38800 44800 4
C 39400 45400 1 270 0 capacitor-1.sym
{
T 40100 45200 5 10 0 1 270 0 1
device=CAPACITOR
T 39400 45400 5 10 0 1 0 0 1
footprint=0603
T 39900 45300 5 10 1 1 180 0 1
refdes=C2
T 40100 44800 5 10 1 1 180 0 1
value=470p
}
N 38800 44400 39600 44400 4
N 39600 44400 39600 44500 4
N 39600 45600 39600 45400 4
C 40200 45400 1 270 0 capacitor-1.sym
{
T 40900 45200 5 10 0 1 270 0 1
device=CAPACITOR
T 40200 45400 5 10 0 1 0 0 1
footprint=0603
T 40700 45300 5 10 1 1 180 0 1
refdes=C4
T 40700 44800 5 10 1 1 180 0 1
value=1u
}
N 40400 45600 40400 45400 4
N 40400 44500 40400 44400 4
N 36800 45200 36500 45200 4
N 36500 44800 36500 45600 4
C 35800 45400 1 270 0 capacitor-1.sym
{
T 36500 45200 5 10 0 1 270 0 1
device=CAPACITOR
T 35800 45400 5 10 0 1 0 0 1
footprint=0603
T 36300 45300 5 10 1 1 180 0 1
refdes=C1
T 36300 44800 5 10 1 1 180 0 1
value=1u
}
N 36800 44800 36500 44800 4
N 36000 45400 36000 45600 4
C 41200 45600 1 0 0 vcc.sym
{
T 41200 47300 5 8 0 0 0 0 1
footprint=none
T 41200 47100 5 8 0 0 0 0 1
symversion=1.0
T 41200 45600 5 10 0 1 0 0 1
net=3V3:1
T 41300 45600 5 10 1 1 0 0 1
value=3V3
}
C 40300 44100 1 0 0 agnd.sym
C 35900 44000 1 0 0 agnd.sym
C 35100 45000 1 0 1 jumper2.sym
{
T 34100 45200 5 8 0 0 0 6 1
device=JUMPER2
T 34100 45000 5 8 0 0 0 6 1
footprint=JUMPER2
T 34700 45900 5 10 1 1 0 6 1
refdes=J1
}
N 35100 45200 35300 45200 4
N 35300 45200 35300 45000 4
C 35200 44700 1 0 0 agnd.sym
N 36800 45600 35100 45600 4