pcb

v 20130925 2
C 39100 69500 1 0 0 MC33063.sym
{
T 41500 72100 5 10 1 1 0 6 1
refdes=U1
T 39500 72300 5 10 0 0 0 0 1
device=MC33063
T 39500 72500 5 10 0 0 0 0 1
footprint=SO8
}
C 39100 64000 1 0 0 MC33063.sym
{
T 41500 66600 5 10 1 1 0 6 1
refdes=U2
T 39500 66800 5 10 0 0 0 0 1
device=MC33063
T 39500 67000 5 10 0 0 0 0 1
footprint=SO8
}
C 35500 71000 1 0 0 schottky-1.sym
{
T 35822 71672 5 10 0 0 0 0 1
device=30BQ060
T 35800 71500 5 10 1 1 0 0 1
refdes=D1
T 35841 71832 5 10 0 1 0 0 1
footprint=30BQ060
}
C 43200 69700 1 90 0 schottky-1.sym
{
T 42528 70022 5 10 0 0 90 0 1
device=10MQ060N
T 42700 70000 5 10 1 1 90 0 1
refdes=D3
T 42368 70041 5 10 0 1 90 0 1
footprint=10MQ060N
}
C 42900 69400 1 0 0 gnd-1.sym
C 37000 61500 1 0 0 header4-2.sym
{
T 37600 62400 5 10 1 1 0 0 1
refdes=J1
T 37000 61500 5 10 0 1 0 0 1
footprint=HEADER4_2
}
C 38700 62100 1 0 0 vcc.sym
{
T 38700 63800 5 8 0 0 0 0 1
footprint=none
T 38700 63600 5 8 0 0 0 0 1
symversion=1.0
T 38700 62100 5 10 0 0 0 0 1
net=VBAT1:1
T 38900 62100 5 10 1 1 0 0 1
value=VBAT1
}
N 38400 61700 38800 61700 4
N 38800 61700 38800 62100 4
N 38400 62100 39600 62100 4
C 42000 61500 1 0 0 header4-2.sym
{
T 42600 62400 5 10 1 1 0 0 1
refdes=J2
T 42000 61500 5 10 0 1 0 0 1
footprint=HEADER4_2
}
C 43700 62100 1 0 0 vcc.sym
{
T 43700 63800 5 8 0 0 0 0 1
footprint=none
T 43700 63600 5 8 0 0 0 0 1
symversion=1.0
T 43700 62100 5 10 0 0 0 0 1
net=VBAT2:1
T 43900 62100 5 10 1 1 0 0 1
value=VBAT2
}
N 43400 61700 43800 61700 4
N 43800 61700 43800 62100 4
N 43400 62100 44700 62100 4
C 35200 71200 1 0 0 vcc.sym
{
T 35200 72900 5 8 0 0 0 0 1
footprint=none
T 35200 72700 5 8 0 0 0 0 1
symversion=1.0
T 35200 71200 5 10 0 0 0 0 1
net=VBAT1:1
T 34700 71200 5 10 1 1 0 0 1
value=VBAT1
}
N 35300 71200 35500 71200 4
N 36400 71200 39200 71200 4
C 35200 65700 1 0 0 vcc.sym
{
T 35200 67400 5 8 0 0 0 0 1
footprint=none
T 35200 67200 5 8 0 0 0 0 1
symversion=1.0
T 35200 65700 5 10 0 0 0 0 1
net=VBAT2:1
T 34700 65700 5 10 1 1 0 0 1
value=VBAT2
}
C 39700 61200 1 90 0 resistor-2.sym
{
T 39350 61600 5 10 0 0 90 0 1
device=RESISTOR
T 39400 61900 5 10 1 1 180 0 1
refdes=R11
T 39200 61500 5 10 1 1 0 0 1
value=4k
T 39700 61200 5 10 0 1 0 0 1
footprint=0603
}
C 40300 60300 1 90 0 capacitor-1.sym
{
T 39600 60500 5 10 0 0 90 0 1
device=CAPACITOR
T 40400 61000 5 10 1 1 180 0 1
refdes=C6
T 39400 60500 5 10 0 0 90 0 1
symversion=0.1
T 40200 60500 5 10 1 1 0 0 1
value=0.1u
T 40300 60300 5 10 0 1 0 0 1
footprint=0603
}
C 39700 60300 1 90 0 resistor-2.sym
{
T 39350 60700 5 10 0 0 90 0 1
device=RESISTOR
T 39400 61000 5 10 1 1 180 0 1
refdes=R12
T 39200 60600 5 10 1 1 0 0 1
value=1k
T 39700 60300 5 10 0 1 0 0 1
footprint=0603
}
C 39500 60000 1 0 0 gnd-1.sym
C 40000 60000 1 0 0 gnd-1.sym
C 40500 61200 1 0 0 vcc.sym
{
T 40500 62900 5 8 0 0 0 0 1
footprint=none
T 40500 62700 5 8 0 0 0 0 1
symversion=1.0
T 40500 61200 5 10 0 0 0 0 1
net=VBAT1A:1
T 40700 61200 5 10 1 1 0 0 1
value=VBAT1A
}
N 39600 61200 40600 61200 4
C 44800 61200 1 90 0 resistor-2.sym
{
T 44450 61600 5 10 0 0 90 0 1
device=RESISTOR
T 44500 61900 5 10 1 1 180 0 1
refdes=R13
T 44300 61500 5 10 1 1 0 0 1
value=4k
T 44800 61200 5 10 0 1 0 0 1
footprint=0603
}
C 45400 60300 1 90 0 capacitor-1.sym
{
T 44700 60500 5 10 0 0 90 0 1
device=CAPACITOR
T 45500 61000 5 10 1 1 180 0 1
refdes=C13
T 44500 60500 5 10 0 0 90 0 1
symversion=0.1
T 45300 60500 5 10 1 1 0 0 1
value=0.1u
T 45400 60300 5 10 0 1 0 0 1
footprint=0603
}
C 44800 60300 1 90 0 resistor-2.sym
{
T 44450 60700 5 10 0 0 90 0 1
device=RESISTOR
T 44500 61000 5 10 1 1 180 0 1
refdes=R14
T 44300 60600 5 10 1 1 0 0 1
value=1k
T 44800 60300 5 10 0 1 0 0 1
footprint=0603
}
C 44600 60000 1 0 0 gnd-1.sym
C 45100 60000 1 0 0 gnd-1.sym
C 45600 61200 1 0 0 vcc.sym
{
T 45600 62900 5 8 0 0 0 0 1
footprint=none
T 45600 62700 5 8 0 0 0 0 1
symversion=1.0
T 45600 61200 5 10 0 0 0 0 1
net=VBAT2A:1
T 45800 61200 5 10 1 1 0 0 1
value=VBAT2A
}
N 44700 61200 45700 61200 4
C 38200 71200 1 90 0 resistor-2.sym
{
T 37850 71600 5 10 0 0 90 0 1
device=RESISTOR
T 37900 71900 5 10 1 1 180 0 1
refdes=R2
T 37800 71500 5 10 1 1 0 0 1
value=1
T 38200 71200 5 10 0 1 0 0 1
footprint=0603
}
C 38800 71200 1 90 0 resistor-2.sym
{
T 38450 71600 5 10 0 0 90 0 1
device=RESISTOR
T 38500 71900 5 10 1 1 180 0 1
refdes=R3
T 38400 71500 5 10 1 1 0 0 1
value=1
T 38800 71200 5 10 0 1 0 0 1
footprint=0603
}
C 37600 71200 1 90 0 resistor-2.sym
{
T 37250 71600 5 10 0 0 90 0 1
device=RESISTOR
T 37300 71900 5 10 1 1 180 0 1
refdes=R1
T 37200 71500 5 10 1 1 0 0 1
value=1
T 37600 71200 5 10 0 1 0 0 1
footprint=0603
}
N 41800 71200 42300 71200 4
N 42300 71200 42300 72500 4
N 37500 72500 42300 72500 4
N 39000 72500 39000 71600 4
N 39000 71600 39200 71600 4
N 37500 72500 37500 72100 4
N 38100 72500 38100 72100 4
N 38700 72100 38700 72500 4
N 41800 71600 42300 71600 4
N 41800 70800 43500 70800 4
N 43000 70800 43000 70600 4
C 43500 70700 1 0 0 inductor-1.sym
{
T 43700 71200 5 10 0 0 0 0 1
device=INDUCTOR
T 43700 71000 5 10 1 1 0 0 1
refdes=L1
T 43700 71400 5 10 0 0 0 0 1
symversion=0.1
T 43600 70600 5 10 1 1 0 0 1
value=100uH
T 43500 70700 5 10 0 1 0 0 1
footprint=B82477G4
}
C 45200 70800 1 0 0 vcc.sym
{
T 45200 72500 5 8 0 0 0 0 1
footprint=none
T 45200 72300 5 8 0 0 0 0 1
symversion=1.0
T 45200 70800 5 10 0 0 0 0 1
net=5V:1
T 45400 70800 5 10 1 1 0 0 1
value=5V
}
N 45300 70800 44400 70800 4
C 44400 70600 1 270 0 capacitor-2.sym
{
T 45100 70400 5 10 0 0 270 0 1
device=POLARIZED_CAPACITOR
T 44200 70300 5 10 1 1 0 0 1
refdes=C5
T 45300 70400 5 10 0 0 270 0 1
symversion=0.1
T 44000 69800 5 10 1 1 0 0 1
value=330u
T 44400 70600 5 10 0 1 0 0 1
footprint=tant_7x4mm
}
C 44500 69400 1 0 0 gnd-1.sym
N 44600 70600 44600 70800 4
C 38500 70900 1 270 0 gnd-1.sym
N 38800 70800 39200 70800 4
C 38700 69000 1 180 0 resistor-2.sym
{
T 38300 68650 5 10 0 0 180 0 1
device=RESISTOR
T 38100 69100 5 10 1 1 0 0 1
refdes=R4
T 38300 68700 5 10 1 1 180 0 1
value=10k
T 38700 69000 5 10 0 1 0 0 1
footprint=0603
}
C 40700 69000 1 180 0 resistor-2.sym
{
T 40300 68650 5 10 0 0 180 0 1
device=RESISTOR
T 40100 69100 5 10 1 1 0 0 1
refdes=R6
T 40300 68700 5 10 1 1 180 0 1
value=30k
T 40700 69000 5 10 0 1 0 0 1
footprint=0603
}
N 39800 68900 38700 68900 4
N 40700 68900 45100 68900 4
N 45100 68900 45100 70800 4
N 39200 70000 38900 70000 4
N 38900 70000 38900 68900 4
C 37400 69000 1 270 0 gnd-1.sym
N 37700 68900 37800 68900 4
C 38500 70600 1 180 0 capacitor-1.sym
{
T 38300 69900 5 10 0 0 180 0 1
device=CAPACITOR
T 37700 70600 5 10 1 1 0 0 1
refdes=C2
T 38300 69700 5 10 0 0 180 0 1
symversion=0.1
T 38000 70200 5 10 1 1 180 0 1
value=390p
T 38500 70600 5 10 0 1 0 0 1
footprint=0603
}
C 37100 70500 1 270 0 gnd-1.sym
N 37400 70400 37600 70400 4
N 38500 70400 39200 70400 4
C 35500 65500 1 0 0 schottky-1.sym
{
T 35822 66172 5 10 0 0 0 0 1
device=30BQ060
T 35800 66000 5 10 1 1 0 0 1
refdes=D2
T 35841 66332 5 10 0 1 0 0 1
footprint=30BQ060
}
C 43200 64200 1 90 0 schottky-1.sym
{
T 42528 64522 5 10 0 0 90 0 1
device=10MQ060N
T 42700 64500 5 10 1 1 90 0 1
refdes=D4
T 42368 64541 5 10 0 1 90 0 1
footprint=10MQ060N
}
C 42900 63900 1 0 0 gnd-1.sym
N 35300 65700 35500 65700 4
N 36400 65700 39200 65700 4
C 38200 65700 1 90 0 resistor-2.sym
{
T 37850 66100 5 10 0 0 90 0 1
device=RESISTOR
T 37900 66400 5 10 1 1 180 0 1
refdes=R7
T 37800 66000 5 10 1 1 0 0 1
value=1
T 38200 65700 5 10 0 1 0 0 1
footprint=0603
}
C 38800 65700 1 90 0 resistor-2.sym
{
T 38450 66100 5 10 0 0 90 0 1
device=RESISTOR
T 38500 66400 5 10 1 1 180 0 1
refdes=R8
T 38400 66000 5 10 1 1 0 0 1
value=1
T 38800 65700 5 10 0 1 0 0 1
footprint=0603
}
C 37600 65700 1 90 0 resistor-2.sym
{
T 37250 66100 5 10 0 0 90 0 1
device=RESISTOR
T 37300 66400 5 10 1 1 180 0 1
refdes=R5
T 37200 66000 5 10 1 1 0 0 1
value=1
T 37600 65700 5 10 0 1 0 0 1
footprint=0603
}
N 41800 65700 42300 65700 4
N 42300 65700 42300 67000 4
N 37500 67000 42300 67000 4
N 39000 67000 39000 66100 4
N 39000 66100 39200 66100 4
N 37500 67000 37500 66600 4
N 38100 67000 38100 66600 4
N 38700 66600 38700 67000 4
N 41800 66100 42300 66100 4
N 41800 65300 43500 65300 4
N 43000 65300 43000 65100 4
C 43500 65200 1 0 0 inductor-1.sym
{
T 43700 65700 5 10 0 0 0 0 1
device=INDUCTOR
T 43700 65500 5 10 1 1 0 0 1
refdes=L2
T 43700 65900 5 10 0 0 0 0 1
symversion=0.1
T 43600 65100 5 10 1 1 0 0 1
value=100uH
T 43500 65200 5 10 0 1 0 0 1
footprint=B82477G4
}
C 45200 65300 1 0 0 vcc.sym
{
T 45200 67000 5 8 0 0 0 0 1
footprint=none
T 45200 66800 5 8 0 0 0 0 1
symversion=1.0
T 45200 65300 5 10 0 0 0 0 1
net=3V3:1
T 45400 65300 5 10 1 1 0 0 1
value=3V3
}
N 45300 65300 44400 65300 4
C 44400 65100 1 270 0 capacitor-2.sym
{
T 45100 64900 5 10 0 0 270 0 1
device=POLARIZED_CAPACITOR
T 44200 64800 5 10 1 1 0 0 1
refdes=C7
T 45300 64900 5 10 0 0 270 0 1
symversion=0.1
T 44000 64300 5 10 1 1 0 0 1
value=330u
T 44400 65100 5 10 0 1 0 0 1
footprint=tant_7x4mm
}
C 44500 63900 1 0 0 gnd-1.sym
N 44600 65100 44600 65300 4
C 38500 65400 1 270 0 gnd-1.sym
N 38800 65300 39200 65300 4
C 38700 63500 1 180 0 resistor-2.sym
{
T 38300 63150 5 10 0 0 180 0 1
device=RESISTOR
T 38100 63600 5 10 1 1 0 0 1
refdes=R9
T 38300 63200 5 10 1 1 180 0 1
value=11k
T 38700 63500 5 10 0 1 0 0 1
footprint=0603
}
C 40700 63500 1 180 0 resistor-2.sym
{
T 40300 63150 5 10 0 0 180 0 1
device=RESISTOR
T 40100 63600 5 10 1 1 0 0 1
refdes=R10
T 40300 63200 5 10 1 1 180 0 1
value=18k
T 40700 63500 5 10 0 1 0 0 1
footprint=0603
}
N 39800 63400 38700 63400 4
N 40700 63400 45100 63400 4
N 45100 63400 45100 65300 4
N 39200 64500 38900 64500 4
N 38900 64500 38900 63400 4
C 37400 63500 1 270 0 gnd-1.sym
N 37700 63400 37800 63400 4
C 38500 65100 1 180 0 capacitor-1.sym
{
T 38300 64400 5 10 0 0 180 0 1
device=CAPACITOR
T 37700 65100 5 10 1 1 0 0 1
refdes=C4
T 38300 64200 5 10 0 0 180 0 1
symversion=0.1
T 38000 64700 5 10 1 1 180 0 1
value=270p
T 38500 65100 5 10 0 1 0 0 1
footprint=0603
}
C 37100 65000 1 270 0 gnd-1.sym
N 37400 64900 37600 64900 4
N 38500 64900 39200 64900 4
N 62700 65300 62700 65000 4
N 62700 65000 65500 65000 4
N 65500 65000 65500 65300 4
N 63100 65300 63100 65000 4
N 63500 65300 63500 65000 4
N 63900 65300 63900 65000 4
N 64300 65300 64300 65000 4
N 64700 65300 64700 65000 4
N 65100 65300 65100 65000 4
C 64000 64700 1 0 0 gnd-1.sym
C 60800 75500 1 0 0 input-1.sym
{
T 60800 75800 5 10 0 0 0 0 1
device=INPUT
T 60800 75500 5 10 0 0 0 0 1
net=RX+:1
T 60400 75500 5 10 1 1 0 0 1
value=RX+
}
N 61600 75600 62000 75600 4
C 60800 75100 1 0 0 input-1.sym
{
T 60800 75400 5 10 0 0 0 0 1
device=INPUT
T 60800 75100 5 10 0 0 0 0 1
net=RX-:1
T 60400 75100 5 10 1 1 0 0 1
value=RX-
}
N 61600 75200 62000 75200 4
C 66500 75500 1 0 0 output-1.sym
{
T 66600 75800 5 10 0 0 0 0 1
device=OUTPUT
T 66500 75500 5 10 0 0 0 0 1
net=TX+:1
T 67300 75500 5 10 1 1 0 0 1
value=TX+
}
N 66500 75600 66100 75600 4
C 66500 75100 1 0 0 output-1.sym
{
T 66600 75400 5 10 0 0 0 0 1
device=OUTPUT
T 66500 75100 5 10 0 0 0 0 1
net=TX-:1
T 67300 75100 5 10 1 1 0 0 1
value=TX-
}
N 66500 75200 66100 75200 4
C 60600 70000 1 0 0 vcc.sym
{
T 60600 71700 5 8 0 0 0 0 1
footprint=none
T 60600 71500 5 8 0 0 0 0 1
symversion=1.0
T 60600 70000 5 10 0 0 0 0 1
net=3V3:1
T 60300 70000 5 10 1 1 0 0 1
value=3V3
}
C 61200 69100 1 90 0 capacitor-1.sym
{
T 60500 69300 5 10 0 0 90 0 1
device=CAPACITOR
T 61300 69800 5 10 1 1 180 0 1
refdes=C18
T 60300 69300 5 10 0 0 90 0 1
symversion=0.1
T 61100 69300 5 10 1 1 0 0 1
value=0.1u
T 61200 69100 5 10 0 1 0 0 1
footprint=0603
}
N 62000 70000 60700 70000 4
N 62000 69600 61600 69600 4
N 61600 69600 61600 70000 4
C 60900 68800 1 0 0 gnd-1.sym
N 60700 67600 62000 67600 4
N 62000 68000 60700 68000 4
C 67400 68500 1 180 0 resistor-2.sym
{
T 67000 68150 5 10 0 0 180 0 1
device=RESISTOR
T 66800 68500 5 10 1 1 0 0 1
refdes=R19
T 67200 68300 5 10 1 1 180 0 1
value=6.49k
T 67400 68500 5 10 0 1 0 0 1
footprint=0603
}
N 66500 68400 66100 68400 4
C 67900 68300 1 90 0 gnd-1.sym
N 67600 68400 67400 68400 4
C 60900 65100 1 90 0 capacitor-1.sym
{
T 60200 65300 5 10 0 0 90 0 1
device=CAPACITOR
T 61000 65800 5 10 1 1 180 0 1
refdes=C21
T 60000 65300 5 10 0 0 90 0 1
symversion=0.1
T 60800 65300 5 10 1 1 0 0 1
value=1u
T 60900 65100 5 10 0 1 0 0 1
footprint=0603
}
N 62000 71200 61500 71200 4
C 67300 74500 1 180 0 input-1.sym
{
T 67300 74200 5 10 0 0 180 0 1
device=INPUT
T 67300 74500 5 10 0 0 180 0 1
net=REFCLK:1
T 67400 74300 5 10 1 1 0 0 1
value=REFCLK
}
N 66500 74400 66100 74400 4
C 67300 70900 1 180 0 input-1.sym
{
T 67300 70600 5 10 0 0 180 0 1
device=INPUT
T 67300 70900 5 10 0 0 180 0 1
net=MDC:1
T 67400 70700 5 10 1 1 0 0 1
value=MDC
}
N 66500 70800 66100 70800 4
C 66500 71100 1 0 0 io-1.sym
{
T 67400 71300 5 10 0 0 0 0 1
net=MDIO:1
T 66700 71700 5 10 0 0 0 0 1
device=none
T 67400 71200 5 10 1 1 0 1 1
value=MDIO
}
N 66500 71200 66100 71200 4
C 67300 73300 1 180 0 input-1.sym
{
T 67300 73000 5 10 0 0 180 0 1
device=INPUT
T 67300 73300 5 10 0 0 180 0 1
net=TXD0:1
T 67400 73100 5 10 1 1 0 0 1
value=TXD0
}
N 66500 73200 66100 73200 4
C 67300 72900 1 180 0 input-1.sym
{
T 67300 72600 5 10 0 0 180 0 1
device=INPUT
T 67300 72900 5 10 0 0 180 0 1
net=TXD1:1
T 67400 72700 5 10 1 1 0 0 1
value=TXD1
}
N 66500 72800 66100 72800 4
C 61600 73300 1 180 0 output-1.sym
{
T 61500 73000 5 10 0 0 180 0 1
device=OUTPUT
T 61600 73300 5 10 0 0 180 0 1
net=RXD0:1
T 60300 73100 5 10 1 1 0 0 1
value=RXD0
}
N 61600 73200 62000 73200 4
C 61600 72900 1 180 0 output-1.sym
{
T 61500 72600 5 10 0 0 180 0 1
device=OUTPUT
T 61600 72900 5 10 0 0 180 0 1
net=RXD1:1
T 60300 72700 5 10 1 1 0 0 1
value=RXD1
}
N 61600 72800 62000 72800 4
C 67300 73700 1 180 0 input-1.sym
{
T 67300 73400 5 10 0 0 180 0 1
device=INPUT
T 67300 73700 5 10 0 0 180 0 1
net=TXEN:1
T 67400 73500 5 10 1 1 0 0 1
value=TXEN
}
N 66500 73600 66100 73600 4
C 67400 70500 1 180 0 resistor-2.sym
{
T 67000 70150 5 10 0 0 180 0 1
device=RESISTOR
T 66800 70500 5 10 1 1 0 0 1
refdes=R15
T 67200 70300 5 10 1 1 180 0 1
value=10k
T 67400 70500 5 10 0 1 0 0 1
footprint=0603
}
N 66100 70400 66500 70400 4
C 60600 68400 1 0 0 vcc.sym
{
T 60600 70100 5 8 0 0 0 0 1
footprint=none
T 60600 69900 5 8 0 0 0 0 1
symversion=1.0
T 60600 68400 5 10 0 0 0 0 1
net=2V5:1
T 60300 68400 5 10 1 1 0 0 1
value=2V5
}
N 68000 70400 67400 70400 4
N 61600 73600 62000 73600 4
C 67300 68100 1 180 0 input-1.sym
{
T 67300 67800 5 10 0 0 180 0 1
device=INPUT
T 67300 68100 5 10 0 0 180 0 1
net=ETH_RESET:1
T 67400 67900 5 10 1 1 0 0 1
value=ETH_RESET
}
C 66500 67100 1 0 0 led-2.sym
{
T 67200 67300 5 10 1 1 0 0 1
refdes=D5
T 66600 67700 5 10 0 0 0 0 1
device=LED
T 66500 67100 5 10 0 1 0 0 1
footprint=0603
}
C 61900 65200 1 0 0 KS8721BL.sym
{
T 65800 76100 5 10 1 1 0 6 1
refdes=U4
T 62300 76300 5 10 0 0 0 0 1
device=KS8721BL
T 62300 76500 5 10 0 0 0 0 1
footprint=LQFP48_7
}
N 66500 68000 66100 68000 4
N 66500 67200 66100 67200 4
C 69600 67200 1 0 0 vcc.sym
{
T 69600 68900 5 8 0 0 0 0 1
footprint=none
T 69600 68700 5 8 0 0 0 0 1
symversion=1.0
T 69600 67200 5 10 0 0 0 0 1
net=2V5:1
T 69800 67200 5 10 1 1 0 0 1
value=2V5
}
C 66500 66700 1 0 0 led-2.sym
{
T 67200 66900 5 10 1 1 0 0 1
refdes=D6
T 66600 67300 5 10 0 0 0 0 1
device=LED
T 66500 66700 5 10 0 1 0 0 1
footprint=0603
}
N 66500 66800 66100 66800 4
C 66500 66300 1 0 0 led-2.sym
{
T 67200 66500 5 10 1 1 0 0 1
refdes=D7
T 66600 66900 5 10 0 0 0 0 1
device=LED
T 66500 66300 5 10 0 1 0 0 1
footprint=0603
}
N 66500 66400 66100 66400 4
C 66500 65900 1 0 0 led-2.sym
{
T 67200 66100 5 10 1 1 0 0 1
refdes=D8
T 66600 66500 5 10 0 0 0 0 1
device=LED
T 66500 65900 5 10 0 1 0 0 1
footprint=0603
}
N 66500 66000 66100 66000 4
N 67400 66000 68100 66000 4
N 69700 66000 69700 67200 4
N 67400 66800 68100 66800 4
N 67400 66400 68100 66400 4
C 65800 59700 1 0 0 vcc.sym
{
T 65800 61400 5 8 0 0 0 0 1
footprint=none
T 65800 61200 5 8 0 0 0 0 1
symversion=1.0
T 65800 59700 5 10 0 0 0 0 1
net=3V3:1
T 66000 59700 5 10 1 1 0 0 1
value=3V3
}
C 66200 59200 1 90 0 gnd-1.sym
C 62300 58800 1 0 0 USRWIFI.sym
{
T 65200 62600 5 10 1 1 0 6 1
refdes=USRWIFI
T 62700 62800 5 10 0 0 0 0 1
device=USRWIFI
T 62700 63000 5 10 0 0 0 0 1
footprint=USRWIFI
}
N 65900 59700 65500 59700 4
N 65900 59300 65500 59300 4
C 61200 60400 1 0 0 input-1.sym
{
T 61200 60700 5 10 0 0 0 0 1
device=INPUT
T 61200 60400 5 10 0 0 0 0 1
net=WIFI_RESET:1
T 60100 60400 5 10 1 1 0 0 1
value=WIFI_RESET
}
N 62000 60500 62400 60500 4
C 69000 67300 1 180 0 resistor-2.sym
{
T 68600 66950 5 10 0 0 180 0 1
device=RESISTOR
T 68200 67300 5 10 1 1 0 0 1
refdes=R21
T 68600 67300 5 10 1 1 0 0 1
value=220
T 69000 67300 5 10 0 1 0 0 1
footprint=0603
}
N 67400 67200 68100 67200 4
N 69000 67200 69700 67200 4
C 69000 66900 1 180 0 resistor-2.sym
{
T 68600 66550 5 10 0 0 180 0 1
device=RESISTOR
T 68200 66900 5 10 1 1 0 0 1
refdes=R22
T 68600 66900 5 10 1 1 0 0 1
value=220
T 69000 66900 5 10 0 1 0 0 1
footprint=0603
}
C 69000 66500 1 180 0 resistor-2.sym
{
T 68600 66150 5 10 0 0 180 0 1
device=RESISTOR
T 68200 66500 5 10 1 1 0 0 1
refdes=R23
T 68600 66500 5 10 1 1 0 0 1
value=220
T 69000 66500 5 10 0 1 0 0 1
footprint=0603
}
C 69000 66100 1 180 0 resistor-2.sym
{
T 68600 65750 5 10 0 0 180 0 1
device=RESISTOR
T 68200 66100 5 10 1 1 0 0 1
refdes=R24
T 68600 66100 5 10 1 1 0 0 1
value=220
T 69000 66100 5 10 0 1 0 0 1
footprint=0603
}
N 69700 66000 69000 66000 4
N 69000 66400 69700 66400 4
N 69000 66800 69700 66800 4
C 61200 60000 1 0 0 input-1.sym
{
T 61200 60300 5 10 0 0 0 0 1
device=INPUT
T 61200 60000 5 10 0 0 0 0 1
net=WIFI_NLINK:1
T 60100 60000 5 10 1 1 0 0 1
value=WIFI_NLINK
}
N 62000 60100 62400 60100 4
C 61200 59600 1 0 0 input-1.sym
{
T 61200 59900 5 10 0 0 0 0 1
device=INPUT
T 61200 59600 5 10 0 0 0 0 1
net=WIFI_NREADY:1
T 59900 59600 5 10 1 1 0 0 1
value=WIFI_NREADY
}
N 62000 59700 62400 59700 4
C 61200 59200 1 0 0 input-1.sym
{
T 61200 59500 5 10 0 0 0 0 1
device=INPUT
T 61200 59200 5 10 0 0 0 0 1
net=WIFI_NRELOAD:1
T 59800 59200 5 10 1 1 0 0 1
value=WIFI_NRELOAD
}
N 62000 59300 62400 59300 4
C 59700 62200 1 180 0 output-1.sym
{
T 59600 61900 5 10 0 0 180 0 1
device=OUTPUT
T 59700 62200 5 10 0 0 180 0 1
net=RX+:1
T 58500 62000 5 10 1 1 0 0 1
value=RX+
}
C 59700 61800 1 180 0 output-1.sym
{
T 59600 61500 5 10 0 0 180 0 1
device=OUTPUT
T 59700 61800 5 10 0 0 180 0 1
net=RX-:1
T 58500 61600 5 10 1 1 0 0 1
value=RX-
}
C 58900 61200 1 0 0 input-1.sym
{
T 58900 61500 5 10 0 0 0 0 1
device=INPUT
T 58900 61200 5 10 0 0 0 0 1
net=TX+:1
T 58500 61200 5 10 1 1 0 0 1
value=TX+
}
C 62300 62300 1 180 0 capacitor-1.sym
{
T 62100 61600 5 10 0 0 180 0 1
device=CAPACITOR
T 61400 62200 5 10 1 1 0 0 1
refdes=C26
T 62100 61400 5 10 0 0 180 0 1
symversion=0.1
T 61900 62200 5 10 1 1 0 0 1
value=0.1u
T 62300 62300 5 10 0 1 0 0 1
footprint=0603
}
C 58900 60800 1 0 0 input-1.sym
{
T 58900 61100 5 10 0 0 0 0 1
device=INPUT
T 58900 60800 5 10 0 0 0 0 1
net=TX-:1
T 58500 60800 5 10 1 1 0 0 1
value=TX-
}
C 61800 61900 1 180 0 capacitor-1.sym
{
T 61600 61200 5 10 0 0 180 0 1
device=CAPACITOR
T 60900 61800 5 10 1 1 0 0 1
refdes=C25
T 61600 61000 5 10 0 0 180 0 1
symversion=0.1
T 61400 61800 5 10 1 1 0 0 1
value=0.1u
T 61800 61900 5 10 0 1 0 0 1
footprint=0603
}
C 61300 61500 1 180 0 capacitor-1.sym
{
T 61100 60800 5 10 0 0 180 0 1
device=CAPACITOR
T 60400 61400 5 10 1 1 0 0 1
refdes=C24
T 61100 60600 5 10 0 0 180 0 1
symversion=0.1
T 60900 61400 5 10 1 1 0 0 1
value=0.1u
T 61300 61500 5 10 0 1 0 0 1
footprint=0603
}
C 60800 61100 1 180 0 capacitor-1.sym
{
T 60600 60400 5 10 0 0 180 0 1
device=CAPACITOR
T 59900 61000 5 10 1 1 0 0 1
refdes=C23
T 60600 60200 5 10 0 0 180 0 1
symversion=0.1
T 60400 61000 5 10 1 1 0 0 1
value=0.1u
T 60800 61100 5 10 0 1 0 0 1
footprint=0603
}
C 61400 62500 1 90 0 resistor-2.sym
{
T 61050 62900 5 10 0 0 90 0 1
device=RESISTOR
T 61400 63000 5 10 1 1 0 0 1
refdes=R20
T 61600 62900 5 10 1 1 180 0 1
value=50
T 61400 62500 5 10 0 1 0 0 1
footprint=0603
}
C 59700 63600 1 0 0 vcc.sym
{
T 59700 65300 5 8 0 0 0 0 1
footprint=none
T 59700 65100 5 8 0 0 0 0 1
symversion=1.0
T 59700 63600 5 10 0 0 0 0 1
net=3V3:1
T 59900 63600 5 10 1 1 0 0 1
value=3V3
}
C 60900 62500 1 90 0 resistor-2.sym
{
T 60550 62900 5 10 0 0 90 0 1
device=RESISTOR
T 60900 63000 5 10 1 1 0 0 1
refdes=R18
T 61100 62900 5 10 1 1 180 0 1
value=50
T 60900 62500 5 10 0 1 0 0 1
footprint=0603
}
C 60400 62500 1 90 0 resistor-2.sym
{
T 60050 62900 5 10 0 0 90 0 1
device=RESISTOR
T 60400 63000 5 10 1 1 0 0 1
refdes=R17
T 60600 62900 5 10 1 1 180 0 1
value=50
T 60400 62500 5 10 0 1 0 0 1
footprint=0603
}
C 59900 62500 1 90 0 resistor-2.sym
{
T 59550 62900 5 10 0 0 90 0 1
device=RESISTOR
T 59900 63000 5 10 1 1 0 0 1
refdes=R16
T 60100 62900 5 10 1 1 180 0 1
value=50
T 59900 62500 5 10 0 1 0 0 1
footprint=0603
}
N 61300 63400 61300 63600 4
N 61300 63600 59800 63600 4
N 59800 63600 59800 63400 4
N 60300 63400 60300 63600 4
N 60800 63400 60800 63600 4
C 62400 53000 1 0 0 OV7670.sym
{
T 64800 58000 5 10 1 1 0 6 1
refdes=U5
T 62800 58200 5 10 0 0 0 0 1
device=OV7670
T 62800 58400 5 10 0 0 0 0 1
footprint=HEADER18_2
}
C 61800 54400 1 270 0 gnd-1.sym
C 62000 54700 1 0 0 vcc.sym
{
T 62000 56400 5 8 0 0 0 0 1
footprint=none
T 62000 56200 5 8 0 0 0 0 1
symversion=1.0
T 62000 54700 5 10 0 0 0 0 1
net=3V3:1
T 61700 54700 5 10 1 1 0 0 1
value=3V3
}
N 62100 54700 62500 54700 4
N 62100 54300 62500 54300 4
C 65500 57400 1 0 0 output-1.sym
{
T 65600 57700 5 10 0 0 0 0 1
device=OUTPUT
T 65500 57400 5 10 0 0 0 0 1
net=VSYNC:1
T 66300 57400 5 10 1 1 0 0 1
value=VSYNC
}
N 65500 57500 65100 57500 4
C 65500 57000 1 0 0 output-1.sym
{
T 65600 57300 5 10 0 0 0 0 1
device=OUTPUT
T 65500 57000 5 10 0 0 0 0 1
net=HSYNC:1
T 66300 57000 5 10 1 1 0 0 1
value=HSYNC
}
N 65500 57100 65100 57100 4
C 65500 56600 1 0 0 output-1.sym
{
T 65600 56900 5 10 0 0 0 0 1
device=OUTPUT
T 65500 56600 5 10 0 0 0 0 1
net=PIXCK:1
T 66300 56600 5 10 1 1 0 0 1
value=PIXCK
}
N 65500 56700 65100 56700 4
C 65500 56200 1 0 0 output-1.sym
{
T 65600 56500 5 10 0 0 0 0 1
device=OUTPUT
T 65500 56200 5 10 0 0 0 0 1
net=D7:1
T 66300 56200 5 10 1 1 0 0 1
value=D7
}
N 65500 56300 65100 56300 4
C 65500 55800 1 0 0 output-1.sym
{
T 65600 56100 5 10 0 0 0 0 1
device=OUTPUT
T 65500 55800 5 10 0 0 0 0 1
net=D6:1
T 66300 55800 5 10 1 1 0 0 1
value=D6
}
N 65500 55900 65100 55900 4
C 65500 55400 1 0 0 output-1.sym
{
T 65600 55700 5 10 0 0 0 0 1
device=OUTPUT
T 65500 55400 5 10 0 0 0 0 1
net=D5:1
T 66300 55400 5 10 1 1 0 0 1
value=D5
}
N 65500 55500 65100 55500 4
C 65500 55000 1 0 0 output-1.sym
{
T 65600 55300 5 10 0 0 0 0 1
device=OUTPUT
T 65500 55000 5 10 0 0 0 0 1
net=D4:1
T 66300 55000 5 10 1 1 0 0 1
value=D4
}
N 65500 55100 65100 55100 4
C 65500 54600 1 0 0 output-1.sym
{
T 65600 54900 5 10 0 0 0 0 1
device=OUTPUT
T 65500 54600 5 10 0 0 0 0 1
net=D3:1
T 66300 54600 5 10 1 1 0 0 1
value=D3
}
N 65500 54700 65100 54700 4
C 65500 54200 1 0 0 output-1.sym
{
T 65600 54500 5 10 0 0 0 0 1
device=OUTPUT
T 65500 54200 5 10 0 0 0 0 1
net=D2:1
T 66300 54200 5 10 1 1 0 0 1
value=D2
}
N 65500 54300 65100 54300 4
C 65500 53800 1 0 0 output-1.sym
{
T 65600 54100 5 10 0 0 0 0 1
device=OUTPUT
T 65500 53800 5 10 0 0 0 0 1
net=D1:1
T 66300 53800 5 10 1 1 0 0 1
value=D1
}
N 65500 53900 65100 53900 4
C 65500 53400 1 0 0 output-1.sym
{
T 65600 53700 5 10 0 0 0 0 1
device=OUTPUT
T 65500 53400 5 10 0 0 0 0 1
net=D0:1
T 66300 53400 5 10 1 1 0 0 1
value=D0
}
N 65500 53500 65100 53500 4
C 61300 56200 1 0 0 input-1.sym
{
T 61300 56500 5 10 0 0 0 0 1
device=INPUT
T 61300 56200 5 10 0 0 0 0 1
net=OV_CLK:1
T 60500 56200 5 10 1 1 0 0 1
value=OV_CLK
}
N 62100 56300 62500 56300 4
C 61300 55800 1 0 0 input-1.sym
{
T 61300 56100 5 10 0 0 0 0 1
device=INPUT
T 61300 55800 5 10 0 0 0 0 1
net=OV_RESET:1
T 60300 55800 5 10 1 1 0 0 1
value=OV_RESET
}
N 62100 55900 62500 55900 4
C 61300 55400 1 0 0 input-1.sym
{
T 61300 55700 5 10 0 0 0 0 1
device=INPUT
T 61300 55400 5 10 0 0 0 0 1
net=OV_PWDN:1
T 60300 55400 5 10 1 1 0 0 1
value=OV_PWDN
}
N 62100 55500 62500 55500 4
C 61300 57400 1 0 0 input-1.sym
{
T 61300 57700 5 10 0 0 0 0 1
device=INPUT
T 61300 57400 5 10 0 0 0 0 1
net=SCL:1
T 60900 57400 5 10 1 1 0 0 1
value=SCL
}
N 62100 57500 62500 57500 4
C 62100 57200 1 180 0 io-1.sym
{
T 61200 57000 5 10 0 0 180 0 1
net=SDA:1
T 61900 56600 5 10 0 0 180 0 1
device=none
T 60900 57100 5 10 1 1 0 1 1
value=SDA
}
N 62100 57100 62500 57100 4
N 77800 49900 79700 49900 4
C 79000 49600 1 270 0 gnd-1.sym
N 79300 49500 79700 49500 4
C 78500 48600 1 0 0 input-1.sym
{
T 78500 48900 5 10 0 0 0 0 1
device=INPUT
T 78500 48600 5 10 0 0 0 0 1
net=SCL:1
T 78100 48600 5 10 1 1 0 0 1
value=SCL
}
N 79300 48700 79700 48700 4
C 79300 49200 1 180 0 io-1.sym
{
T 78400 49000 5 10 0 0 180 0 1
net=SDA:1
T 79100 48600 5 10 0 0 180 0 1
device=none
T 78100 49100 5 10 1 1 0 1 1
value=SDA
}
N 79300 49100 79700 49100 4
N 41700 50200 42100 50200 4
C 41400 49900 1 270 0 gnd-1.sym
N 41700 49800 42100 49800 4
C 40900 48900 1 0 0 input-1.sym
{
T 40900 49200 5 10 0 0 0 0 1
device=INPUT
T 40900 48900 5 10 0 0 0 0 1
net=ECHO:1
T 40300 48900 5 10 1 1 0 0 1
value=ECHO
}
N 41700 49000 42100 49000 4
C 41700 49500 1 180 0 output-1.sym
{
T 41600 49200 5 10 0 0 180 0 1
device=OUTPUT
T 41700 49500 5 10 0 0 180 0 1
net=TRIG:1
T 40400 49300 5 10 1 1 0 0 1
value=TRIG
}
N 41700 49400 42100 49400 4
C 41600 50200 1 0 0 vcc.sym
{
T 41600 51900 5 8 0 0 0 0 1
footprint=none
T 41600 51700 5 8 0 0 0 0 1
symversion=1.0
T 41600 50200 5 10 0 0 0 0 1
net=5V:1
T 41400 50200 5 10 1 1 0 0 1
value=5V
}
C 45100 57000 1 270 0 gnd-1.sym
C 45100 55700 1 270 0 gnd-1.sym
C 45100 54400 1 270 0 gnd-1.sym
C 45100 53100 1 270 0 gnd-1.sym
C 35500 50200 1 0 0 vcc.sym
{
T 35500 51900 5 8 0 0 0 0 1
footprint=none
T 35500 51700 5 8 0 0 0 0 1
symversion=1.0
T 35500 50200 5 10 0 0 0 0 1
net=3V3:1
T 35200 50200 5 10 1 1 0 0 1
value=3V3
}
N 35600 50200 36000 50200 4
C 35300 49900 1 270 0 gnd-1.sym
N 35600 49800 36000 49800 4
C 35600 49500 1 180 0 output-1.sym
{
T 35500 49200 5 10 0 0 180 0 1
device=OUTPUT
T 35600 49500 5 10 0 0 180 0 1
net=UART5_RX:1
T 33700 49300 5 10 1 1 0 0 1
value=UART5_RX
}
N 35600 49400 36000 49400 4
C 34800 48900 1 0 0 input-1.sym
{
T 34800 49200 5 10 0 0 0 0 1
device=INPUT
T 34800 48900 5 10 0 0 0 0 1
net=UART5_TX:1
T 33700 48900 5 10 1 1 0 0 1
value=UART5_TX
}
N 35600 49000 36000 49000 4
C 48500 72900 1 0 0 vcc.sym
{
T 48500 74600 5 8 0 0 0 0 1
footprint=none
T 48500 74400 5 8 0 0 0 0 1
symversion=1.0
T 48500 72900 5 10 0 0 0 0 1
net=5V:1
T 48300 72900 5 10 1 1 0 0 1
value=5V
}
N 50200 70500 49800 70500 4
N 49800 70500 49800 70900 4
N 49800 70900 50200 70900 4
C 49500 71000 1 270 0 gnd-1.sym
N 49800 67700 50200 67700 4
N 49800 67300 50200 67300 4
N 49800 66900 50200 66900 4
N 49800 66500 50200 66500 4
C 49000 67600 1 0 0 input-1.sym
{
T 49000 67900 5 10 0 0 0 0 1
device=INPUT
T 49000 67600 5 10 0 0 0 0 1
net=PIXCK:1
T 48900 67800 5 10 1 1 180 0 1
value=PIXCK
}
C 49000 67200 1 0 0 input-1.sym
{
T 49000 67500 5 10 0 0 0 0 1
device=INPUT
T 49000 67200 5 10 0 0 0 0 1
net=HSYNC:1
T 48900 67400 5 10 1 1 180 0 1
value=HSYNC
}
C 49000 66800 1 0 0 input-1.sym
{
T 49000 67100 5 10 0 0 0 0 1
device=INPUT
T 49000 66800 5 10 0 0 0 0 1
net=VSYNC:1
T 48900 67000 5 10 1 1 180 0 1
value=VSYNC
}
C 49000 66400 1 0 0 input-1.sym
{
T 49000 66700 5 10 0 0 0 0 1
device=INPUT
T 49000 66400 5 10 0 0 0 0 1
net=D0:1
T 48900 66600 5 10 1 1 180 0 1
value=D0
}
C 49000 66000 1 0 0 input-1.sym
{
T 49000 66300 5 10 0 0 0 0 1
device=INPUT
T 49000 66000 5 10 0 0 0 0 1
net=D1:1
T 48900 66200 5 10 1 1 180 0 1
value=D1
}
N 49800 66100 50200 66100 4
C 49000 65600 1 0 0 input-1.sym
{
T 49000 65900 5 10 0 0 0 0 1
device=INPUT
T 49000 65600 5 10 0 0 0 0 1
net=D2:1
T 48900 65800 5 10 1 1 180 0 1
value=D2
}
N 49800 65700 50200 65700 4
C 49000 65200 1 0 0 input-1.sym
{
T 49000 65500 5 10 0 0 0 0 1
device=INPUT
T 49000 65200 5 10 0 0 0 0 1
net=D3:1
T 48900 65400 5 10 1 1 180 0 1
value=D3
}
N 49800 65300 50200 65300 4
C 49000 64800 1 0 0 input-1.sym
{
T 49000 65100 5 10 0 0 0 0 1
device=INPUT
T 49000 64800 5 10 0 0 0 0 1
net=D4:1
T 48900 65000 5 10 1 1 180 0 1
value=D4
}
N 49800 64900 50200 64900 4
C 49000 64400 1 0 0 input-1.sym
{
T 49000 64700 5 10 0 0 0 0 1
device=INPUT
T 49000 64400 5 10 0 0 0 0 1
net=D5:1
T 48900 64600 5 10 1 1 180 0 1
value=D5
}
N 49800 64500 50200 64500 4
C 49000 64000 1 0 0 input-1.sym
{
T 49000 64300 5 10 0 0 0 0 1
device=INPUT
T 49000 64000 5 10 0 0 0 0 1
net=D6:1
T 48900 64200 5 10 1 1 180 0 1
value=D6
}
N 49800 64100 50200 64100 4
C 49000 63600 1 0 0 input-1.sym
{
T 49000 63900 5 10 0 0 0 0 1
device=INPUT
T 49000 63600 5 10 0 0 0 0 1
net=D7:1
T 48900 63800 5 10 1 1 180 0 1
value=D7
}
N 49800 63700 50200 63700 4
C 49800 63400 1 180 0 output-1.sym
{
T 49700 63100 5 10 0 0 180 0 1
device=OUTPUT
T 49800 63400 5 10 0 0 180 0 1
net=OV_CLK:1
T 48200 63200 5 10 1 1 0 0 1
value=OV_CLK
}
N 49800 63300 50200 63300 4
C 49800 61800 1 180 0 io-1.sym
{
T 48900 61600 5 10 0 0 180 0 1
net=MDIO:1
T 49600 61200 5 10 0 0 180 0 1
device=none
T 48500 61700 5 10 1 1 0 1 1
value=MDIO
}
C 49800 62200 1 180 0 output-1.sym
{
T 49700 61900 5 10 0 0 180 0 1
device=OUTPUT
T 49800 62200 5 10 0 0 180 0 1
net=MDC:1
T 48500 62000 5 10 1 1 0 0 1
value=MDC
}
C 49000 60800 1 0 0 input-1.sym
{
T 49000 61100 5 10 0 0 0 0 1
device=INPUT
T 49000 60800 5 10 0 0 0 0 1
net=RXD0:1
T 48500 60800 5 10 1 1 0 0 1
value=RXD0
}
N 49800 60900 50200 60900 4
C 49000 60400 1 0 0 input-1.sym
{
T 49000 60700 5 10 0 0 0 0 1
device=INPUT
T 49000 60400 5 10 0 0 0 0 1
net=RXD1:1
T 48500 60400 5 10 1 1 0 0 1
value=RXD1
}
N 49800 60500 50200 60500 4
N 49800 62100 50200 62100 4
N 49800 61300 50200 61300 4
N 49800 61700 50200 61700 4
C 49000 61200 1 0 0 input-1.sym
{
T 49000 61500 5 10 0 0 0 0 1
device=INPUT
T 49000 61200 5 10 0 0 0 0 1
net=CRSDV:1
T 48300 61200 5 10 1 1 0 0 1
value=CRSDV
}
C 61600 73700 1 180 0 output-1.sym
{
T 61500 73400 5 10 0 0 180 0 1
device=OUTPUT
T 61600 73700 5 10 0 0 180 0 1
net=CRSDV:1
T 60100 73500 5 10 1 1 0 0 1
value=CRSDV
}
C 49800 60200 1 180 0 output-1.sym
{
T 49700 59900 5 10 0 0 180 0 1
device=OUTPUT
T 49800 60200 5 10 0 0 180 0 1
net=TXEN:1
T 48500 60000 5 10 1 1 0 0 1
value=TXEN
}
N 49800 60100 50200 60100 4
C 49800 59800 1 180 0 output-1.sym
{
T 49700 59500 5 10 0 0 180 0 1
device=OUTPUT
T 49800 59800 5 10 0 0 180 0 1
net=TXD0:1
T 48500 59600 5 10 1 1 0 0 1
value=TXD0
}
N 49800 59700 50200 59700 4
C 49800 59400 1 180 0 output-1.sym
{
T 49700 59100 5 10 0 0 180 0 1
device=OUTPUT
T 49800 59400 5 10 0 0 180 0 1
net=TXD1:1
T 48500 59200 5 10 1 1 0 0 1
value=TXD1
}
N 49800 59300 50200 59300 4
C 49000 62400 1 0 0 input-1.sym
{
T 49000 62700 5 10 0 0 0 0 1
device=INPUT
T 49000 62400 5 10 0 0 0 0 1
net=REFCLK:1
T 48200 62400 5 10 1 1 0 0 1
value=REFCLK
}
N 49800 62500 50200 62500 4
C 49800 58600 1 180 0 output-1.sym
{
T 49700 58300 5 10 0 0 180 0 1
device=OUTPUT
T 49800 58600 5 10 0 0 180 0 1
net=CH1:1
T 48600 58400 5 10 1 1 0 0 1
value=CH1
}
N 49800 58500 50200 58500 4
C 49800 58200 1 180 0 output-1.sym
{
T 49700 57900 5 10 0 0 180 0 1
device=OUTPUT
T 49800 58200 5 10 0 0 180 0 1
net=CH2:1
T 48600 58000 5 10 1 1 0 0 1
value=CH2
}
N 49800 58100 50200 58100 4
C 49800 57800 1 180 0 output-1.sym
{
T 49700 57500 5 10 0 0 180 0 1
device=OUTPUT
T 49800 57800 5 10 0 0 180 0 1
net=CH3:1
T 48600 57600 5 10 1 1 0 0 1
value=CH3
}
N 49800 57700 50200 57700 4
C 49800 57400 1 180 0 output-1.sym
{
T 49700 57100 5 10 0 0 180 0 1
device=OUTPUT
T 49800 57400 5 10 0 0 180 0 1
net=CH4:1
T 48600 57200 5 10 1 1 0 0 1
value=CH4
}
N 49800 57300 50200 57300 4
C 49800 56600 1 180 0 output-1.sym
{
T 49700 56300 5 10 0 0 180 0 1
device=OUTPUT
T 49800 56600 5 10 0 0 180 0 1
net=TRIG:1
T 48500 56400 5 10 1 1 0 0 1
value=TRIG
}
N 49800 56500 50200 56500 4
C 49000 56000 1 0 0 input-1.sym
{
T 49000 56300 5 10 0 0 0 0 1
device=INPUT
T 49000 56000 5 10 0 0 0 0 1
net=ECHO:1
T 48400 56000 5 10 1 1 0 0 1
value=ECHO
}
N 49800 56100 50200 56100 4
C 49800 55400 1 180 0 output-1.sym
{
T 49700 55100 5 10 0 0 180 0 1
device=OUTPUT
T 49800 55400 5 10 0 0 180 0 1
net=SCL:1
T 48600 55200 5 10 1 1 0 0 1
value=SCL
}
N 49800 55300 50200 55300 4
N 49800 54900 50200 54900 4
C 49800 55000 1 180 0 io-1.sym
{
T 48900 54800 5 10 0 0 180 0 1
net=SDA:1
T 49600 54400 5 10 0 0 180 0 1
device=none
T 48600 54900 5 10 1 1 0 1 1
value=SDA
}
C 49800 54200 1 180 0 output-1.sym
{
T 49700 53900 5 10 0 0 180 0 1
device=OUTPUT
T 49800 54200 5 10 0 0 180 0 1
net=UART4_TX:1
T 48000 54000 5 10 1 1 0 0 1
value=UART4_TX
}
N 49800 54100 50200 54100 4
C 49000 53600 1 0 0 input-1.sym
{
T 49000 53900 5 10 0 0 0 0 1
device=INPUT
T 49000 53600 5 10 0 0 0 0 1
net=UART4_RX:1
T 48000 53600 5 10 1 1 0 0 1
value=UART4_RX
}
N 49800 53700 50200 53700 4
C 49800 53000 1 180 0 output-1.sym
{
T 49700 52700 5 10 0 0 180 0 1
device=OUTPUT
T 49800 53000 5 10 0 0 180 0 1
net=UART5_TX:1
T 48000 52800 5 10 1 1 0 0 1
value=UART5_TX
}
N 49800 52900 50200 52900 4
C 49000 52400 1 0 0 input-1.sym
{
T 49000 52700 5 10 0 0 0 0 1
device=INPUT
T 49000 52400 5 10 0 0 0 0 1
net=UART5_RX:1
T 48000 52400 5 10 1 1 0 0 1
value=UART5_RX
}
N 49800 52500 50200 52500 4
C 55200 50800 1 0 0 output-1.sym
{
T 55300 51100 5 10 0 0 0 0 1
device=OUTPUT
T 55200 50800 5 10 0 0 0 0 1
net=RFC_NSS:1
T 56000 50800 5 10 1 1 0 0 1
value=RFC_NSS
}
C 49800 51800 1 180 0 output-1.sym
{
T 49700 51500 5 10 0 0 180 0 1
device=OUTPUT
T 49800 51800 5 10 0 0 180 0 1
net=SPI1_SCK:1
T 48100 51600 5 10 1 1 0 0 1
value=SPI1_SCK
}
N 49800 51700 50200 51700 4
C 49000 51200 1 0 0 input-1.sym
{
T 49000 51500 5 10 0 0 0 0 1
device=INPUT
T 49000 51200 5 10 0 0 0 0 1
net=SPI1_MISO:1
T 48000 51200 5 10 1 1 0 0 1
value=SPI1_MISO
}
N 49800 51300 50200 51300 4
C 49800 51000 1 180 0 output-1.sym
{
T 49700 50700 5 10 0 0 180 0 1
device=OUTPUT
T 49800 51000 5 10 0 0 180 0 1
net=SPI1_MOSI:1
T 48000 50800 5 10 1 1 0 0 1
value=SPI1_MOSI
}
N 49800 50900 50200 50900 4
C 49000 50000 1 0 0 input-1.sym
{
T 49000 50300 5 10 0 0 0 0 1
device=INPUT
T 49000 50000 5 10 0 0 0 0 1
net=VBAT1A:1
T 48200 50000 5 10 1 1 0 0 1
value=VBAT1A
}
N 49800 50100 50200 50100 4
C 49000 49600 1 0 0 input-1.sym
{
T 49000 49900 5 10 0 0 0 0 1
device=INPUT
T 49000 49600 5 10 0 0 0 0 1
net=VBAT2A:1
T 48200 49600 5 10 1 1 0 0 1
value=VBAT2A
}
N 49800 49700 50200 49700 4
C 42300 58200 1 0 1 header4-2.sym
{
T 42000 59100 5 10 1 1 0 6 1
refdes=KXOV97
T 42300 58200 5 10 0 1 0 0 1
footprint=KXOV97
T 42300 58200 5 10 0 1 0 0 1
device=KXOV97
}
C 40300 58200 1 90 0 capacitor-1.sym
{
T 39600 58400 5 10 0 0 90 0 1
device=CAPACITOR
T 39900 58900 5 10 1 1 180 0 1
refdes=C8
T 39400 58400 5 10 0 0 90 0 1
symversion=0.1
T 39600 58400 5 10 1 1 0 0 1
value=0.01u
T 40300 58200 5 10 0 1 0 0 1
footprint=0603
}
N 40900 58800 40600 58800 4
N 40600 58800 40600 59100 4
N 39400 59100 40600 59100 4
N 39200 58200 40600 58200 4
N 40600 58200 40600 58400 4
N 40600 58400 40900 58400 4
C 39100 59200 1 270 0 gnd-1.sym
C 39100 58200 1 0 0 vcc.sym
{
T 39100 59900 5 8 0 0 0 0 1
footprint=none
T 39100 59700 5 8 0 0 0 0 1
symversion=1.0
T 39100 58200 5 10 0 0 0 0 1
net=3V3:1
T 38800 58200 5 10 1 1 0 0 1
value=3V3
}
N 42300 58400 43100 58400 4
C 43100 58300 1 0 0 output-1.sym
{
T 43200 58600 5 10 0 0 0 0 1
device=OUTPUT
T 43100 58300 5 10 0 0 0 0 1
net=REFCLK:1
T 43900 58300 5 10 1 1 0 0 1
value=REFCLK
}
C 66700 61800 1 180 0 input-1.sym
{
T 66700 61500 5 10 0 0 180 0 1
device=INPUT
T 66700 61800 5 10 0 0 180 0 1
net=UART4_TX:1
T 66800 61600 5 10 1 1 0 0 1
value=UART4_TX
}
N 65900 61700 65500 61700 4
C 65900 62000 1 0 0 output-1.sym
{
T 66000 62300 5 10 0 0 0 0 1
device=OUTPUT
T 65900 62000 5 10 0 0 0 0 1
net=UART4_RX:1
T 66800 62000 5 10 1 1 0 0 1
value=UART4_RX
}
N 65900 62100 65500 62100 4
C 55200 52000 1 0 0 output-1.sym
{
T 55300 52300 5 10 0 0 0 0 1
device=OUTPUT
T 55200 52000 5 10 0 0 0 0 1
net=LED1:1
T 56000 52000 5 10 1 1 0 0 1
value=LED1
}
N 55200 52100 54800 52100 4
C 55200 52800 1 0 0 output-1.sym
{
T 55300 53100 5 10 0 0 0 0 1
device=OUTPUT
T 55200 52800 5 10 0 0 0 0 1
net=LED2:1
T 56000 52800 5 10 1 1 0 0 1
value=LED2
}
N 55200 52900 54800 52900 4
C 55200 56000 1 0 0 output-1.sym
{
T 55300 56300 5 10 0 0 0 0 1
device=OUTPUT
T 55200 56000 5 10 0 0 0 0 1
net=VCCGSP:1
T 56000 56000 5 10 1 1 0 0 1
value=VCCGSP
}
N 55200 56100 54800 56100 4
C 55200 51200 1 0 0 output-1.sym
{
T 55300 51500 5 10 0 0 0 0 1
device=OUTPUT
T 55200 51200 5 10 0 0 0 0 1
net=WIFI_NLINK:1
T 56000 51200 5 10 1 1 0 0 1
value=WIFI_NLINK
}
N 55200 51300 54800 51300 4
C 55200 55200 1 0 0 output-1.sym
{
T 55300 55500 5 10 0 0 0 0 1
device=OUTPUT
T 55200 55200 5 10 0 0 0 0 1
net=WIFI_NREADY:1
T 56000 55200 5 10 1 1 0 0 1
value=WIFI_NREADY
}
N 55200 55300 54800 55300 4
C 55200 51600 1 0 0 output-1.sym
{
T 55300 51900 5 10 0 0 0 0 1
device=OUTPUT
T 55200 51600 5 10 0 0 0 0 1
net=WIFI_NRELOAD:1
T 56000 51600 5 10 1 1 0 0 1
value=WIFI_NRELOAD
}
N 55200 51700 54800 51700 4
C 55200 53600 1 0 0 output-1.sym
{
T 55300 53900 5 10 0 0 0 0 1
device=OUTPUT
T 55200 53600 5 10 0 0 0 0 1
net=OV_RESET:1
T 56000 53600 5 10 1 1 0 0 1
value=OV_RESET
}
N 55200 53700 54800 53700 4
C 55200 54000 1 0 0 output-1.sym
{
T 55300 54300 5 10 0 0 0 0 1
device=OUTPUT
T 55200 54000 5 10 0 0 0 0 1
net=OV_PWDN:1
T 56000 54000 5 10 1 1 0 0 1
value=OV_PWDN
}
N 55200 54100 54800 54100 4
C 55200 54800 1 0 0 output-1.sym
{
T 55300 55100 5 10 0 0 0 0 1
device=OUTPUT
T 55200 54800 5 10 0 0 0 0 1
net=ETH_RESET:1
T 56000 54800 5 10 1 1 0 0 1
value=ETH_RESET
}
N 55200 54900 54800 54900 4
C 61700 47800 1 0 0 header18-2.sym
{
T 61750 47150 5 10 0 1 0 0 1
device=HEADER18
T 62100 51500 5 10 1 1 0 0 1
refdes=RFC_30F
T 61700 47800 5 10 0 1 0 0 1
footprint=RFC30F
}
C 61200 51200 1 0 0 vcc.sym
{
T 61200 52900 5 8 0 0 0 0 1
footprint=none
T 61200 52700 5 8 0 0 0 0 1
symversion=1.0
T 61200 51200 5 10 0 0 0 0 1
net=5V:1
T 61000 51200 5 10 1 1 0 0 1
value=5V
}
N 61700 51200 61300 51200 4
N 61700 50800 61300 50800 4
N 61300 50800 61300 51200 4
C 63800 51100 1 90 0 gnd-1.sym
N 63100 50800 63500 50800 4
N 63500 50800 63500 51200 4
N 63100 51200 63500 51200 4
C 61200 50400 1 0 0 vcc.sym
{
T 61200 52100 5 8 0 0 0 0 1
footprint=none
T 61200 51900 5 8 0 0 0 0 1
symversion=1.0
T 61200 50400 5 10 0 0 0 0 1
net=3V3:1
T 60900 50400 5 10 1 1 0 0 1
value=3V3
}
C 63800 47900 1 90 0 gnd-1.sym
N 63500 48000 63100 48000 4
C 61000 48100 1 270 0 gnd-1.sym
N 61300 48000 61700 48000 4
C 60500 48300 1 0 0 input-1.sym
{
T 60500 48600 5 10 0 0 0 0 1
device=INPUT
T 60500 48300 5 10 0 0 0 0 1
net=SPI1_SCK:1
T 59600 48300 5 10 1 1 0 0 1
value=SPI1_SCK
}
C 64300 48500 1 180 0 input-1.sym
{
T 64300 48200 5 10 0 0 180 0 1
device=INPUT
T 64300 48500 5 10 0 0 180 0 1
net=RFC_NSS:1
T 64300 48300 5 10 1 1 0 0 1
value=RFC_NSS
}
N 63500 48400 63100 48400 4
C 64300 48900 1 180 0 input-1.sym
{
T 64300 48600 5 10 0 0 180 0 1
device=INPUT
T 64300 48900 5 10 0 0 180 0 1
net=SPI1_MOSI:1
T 64300 48700 5 10 1 1 0 0 1
value=SPI1_MOSI
}
N 63500 48800 63100 48800 4
C 61300 48900 1 180 0 output-1.sym
{
T 61200 48600 5 10 0 0 180 0 1
device=OUTPUT
T 61300 48900 5 10 0 0 180 0 1
net=SPI1_MISO:1
T 59500 48700 5 10 1 1 0 0 1
value=SPI1_MISO
}
N 61300 48800 61700 48800 4
N 61300 48400 61700 48400 4
C 64300 50500 1 180 0 input-1.sym
{
T 64300 50200 5 10 0 0 180 0 1
device=INPUT
T 64300 50500 5 10 0 0 180 0 1
net=RFC_TXEN:1
T 64300 50300 5 10 1 1 0 0 1
value=RFC_TXEN
}
N 63500 50400 63100 50400 4
C 64300 50100 1 180 0 input-1.sym
{
T 64300 49800 5 10 0 0 180 0 1
device=INPUT
T 64300 50100 5 10 0 0 180 0 1
net=RFC_PWRUP:1
T 64300 49900 5 10 1 1 0 0 1
value=RFC_PWRUP
}
N 63500 50000 63100 50000 4
C 60500 49900 1 0 0 input-1.sym
{
T 60500 50200 5 10 0 0 0 0 1
device=INPUT
T 60500 49900 5 10 0 0 0 0 1
net=RFC_TRXCE:1
T 59300 49900 5 10 1 1 0 0 1
value=RFC_TRXCE
}
N 61300 50000 61700 50000 4
C 63500 49500 1 0 0 output-1.sym
{
T 63600 49800 5 10 0 0 0 0 1
device=OUTPUT
T 63500 49500 5 10 0 0 0 0 1
net=RFC_CD:1
T 64300 49500 5 10 1 1 0 0 1
value=RFC_CD
}
N 63500 49600 63100 49600 4
C 63500 49100 1 0 0 output-1.sym
{
T 63600 49400 5 10 0 0 0 0 1
device=OUTPUT
T 63500 49100 5 10 0 0 0 0 1
net=RFC_DR:1
T 64300 49100 5 10 1 1 0 0 1
value=RFC_DR
}
N 63500 49200 63100 49200 4
C 61300 49300 1 180 0 output-1.sym
{
T 61200 49000 5 10 0 0 180 0 1
device=OUTPUT
T 61300 49300 5 10 0 0 180 0 1
net=RFC_AM:1
T 59700 49100 5 10 1 1 0 0 1
value=RFC_AM
}
N 61300 49200 61700 49200 4
C 55200 52400 1 0 0 output-1.sym
{
T 55300 52700 5 10 0 0 0 0 1
device=OUTPUT
T 55200 52400 5 10 0 0 0 0 1
net=RFC_TXEN:1
T 56000 52400 5 10 1 1 0 0 1
value=RFC_TXEN
}
N 55200 52500 54800 52500 4
C 55200 48800 1 0 0 output-1.sym
{
T 55300 49100 5 10 0 0 0 0 1
device=OUTPUT
T 55200 48800 5 10 0 0 0 0 1
net=RFC_PWRUP:1
T 56000 48800 5 10 1 1 0 0 1
value=RFC_PWRUP
}
N 55200 48900 54800 48900 4
C 55200 48400 1 0 0 output-1.sym
{
T 55300 48700 5 10 0 0 0 0 1
device=OUTPUT
T 55200 48400 5 10 0 0 0 0 1
net=RFC_TRXCE:1
T 56000 48400 5 10 1 1 0 0 1
value=RFC_TRXCE
}
N 55200 48500 54800 48500 4
C 56000 54600 1 180 0 input-1.sym
{
T 56000 54300 5 10 0 0 180 0 1
device=INPUT
T 56000 54600 5 10 0 0 180 0 1
net=RFC_CD:1
T 56800 54600 5 10 1 1 180 0 1
value=RFC_CD
}
N 55200 54500 54800 54500 4
C 56000 49400 1 180 0 input-1.sym
{
T 56000 49100 5 10 0 0 180 0 1
device=INPUT
T 56000 49400 5 10 0 0 180 0 1
net=RFC_DR:1
T 56800 49400 5 10 1 1 180 0 1
value=RFC_DR
}
N 55200 49300 54800 49300 4
C 56000 49800 1 180 0 input-1.sym
{
T 56000 49500 5 10 0 0 180 0 1
device=INPUT
T 56000 49800 5 10 0 0 180 0 1
net=RFC_AM:1
T 56800 49800 5 10 1 1 180 0 1
value=RFC_AM
}
N 55200 49700 54800 49700 4
N 41600 62100 41600 61700 4
N 36600 62100 36600 61700 4
C 36800 69200 1 180 0 capacitor-2.sym
{
T 36600 68500 5 10 0 0 180 0 1
device=POLARIZED_CAPACITOR
T 35900 69200 5 10 1 1 0 0 1
refdes=C1
T 36600 68300 5 10 0 0 180 0 1
symversion=0.1
T 36300 69200 5 10 1 1 0 0 1
value=1000u
T 36800 69200 5 10 0 1 0 0 1
footprint=RCY200
}
C 35600 69100 1 270 0 gnd-1.sym
C 36800 68200 1 180 0 capacitor-2.sym
{
T 36600 67500 5 10 0 0 180 0 1
device=POLARIZED_CAPACITOR
T 35900 68200 5 10 1 1 0 0 1
refdes=C3
T 36600 67300 5 10 0 0 180 0 1
symversion=0.1
T 36300 68200 5 10 1 1 0 0 1
value=1000u
T 36800 68200 5 10 0 1 0 0 1
footprint=RCY200
}
C 35600 68100 1 270 0 gnd-1.sym
N 36800 71200 36800 65700 4
C 36000 48800 1 0 0 jumper4.sym
{
T 37000 49800 5 8 0 0 0 0 1
device=JUMPER4
T 36400 50500 5 10 1 1 0 0 1
refdes=GPS
T 37000 49600 5 8 0 0 0 0 1
footprint=JUMPER4
}
C 79700 48500 1 0 0 jumper4.sym
{
T 80700 49500 5 8 0 0 0 0 1
device=JUMPER4
T 80100 50200 5 10 1 1 0 0 1
refdes=GSP
T 80700 49300 5 8 0 0 0 0 1
footprint=JUMPER4
}
C 42100 48800 1 0 0 jumper4.sym
{
T 43100 49800 5 8 0 0 0 0 1
device=JUMPER4
T 42500 50500 5 10 1 1 0 0 1
refdes=HCSR
T 43100 49600 5 8 0 0 0 0 1
footprint=JUMPER4
}
C 45200 50700 1 270 0 gnd-1.sym
C 45400 51000 1 0 0 vcc.sym
{
T 45400 52700 5 8 0 0 0 0 1
footprint=none
T 45400 52500 5 8 0 0 0 0 1
symversion=1.0
T 45400 51000 5 10 0 0 0 0 1
net=5V:1
T 45200 51000 5 10 1 1 0 0 1
value=5V
}
N 45500 51000 45900 51000 4
N 45500 50600 45900 50600 4
C 45500 48700 1 180 0 output-1.sym
{
T 45400 48400 5 10 0 0 180 0 1
device=OUTPUT
T 45500 48700 5 10 0 0 180 0 1
net=SPI1_MISO:1
T 43700 48500 5 10 1 1 0 0 1
value=SPI1_MISO
}
N 45500 48600 45900 48600 4
C 44700 49300 1 0 0 input-1.sym
{
T 44700 49600 5 10 0 0 0 0 1
device=INPUT
T 44700 49300 5 10 0 0 0 0 1
net=SPI1_SCK:1
T 43800 49300 5 10 1 1 0 0 1
value=SPI1_SCK
}
N 45500 49400 45900 49400 4
C 44700 48900 1 0 0 input-1.sym
{
T 44700 49200 5 10 0 0 0 0 1
device=INPUT
T 44700 48900 5 10 0 0 0 0 1
net=SPI1_MOSI:1
T 43700 48900 5 10 1 1 0 0 1
value=SPI1_MOSI
}
N 45500 49000 45900 49000 4
C 44700 50100 1 0 0 input-1.sym
{
T 44700 50400 5 10 0 0 0 0 1
device=INPUT
T 44700 50100 5 10 0 0 0 0 1
net=SS1:1
T 44300 50100 5 10 1 1 0 0 1
value=SS1
}
N 45500 50200 45900 50200 4
C 36500 61400 1 0 0 gnd-1.sym
C 41500 61400 1 0 0 gnd-1.sym
N 36600 62100 37000 62100 4
N 37000 61700 36600 61700 4
N 42000 61700 41600 61700 4
N 41600 62100 42000 62100 4
N 59700 61300 60400 61300 4
N 59700 61700 60900 61700 4
N 59700 62100 61400 62100 4
N 61800 61700 62400 61700 4
N 61300 61300 62400 61300 4
N 60800 60900 62400 60900 4
N 59900 60900 59700 60900 4
N 61300 62500 61300 62100 4
N 60800 62500 60800 61700 4
N 60300 62500 60300 61300 4
N 59800 62500 59800 60900 4
N 62300 62100 62400 62100 4
C 67900 70400 1 0 0 vcc.sym
{
T 67900 72100 5 8 0 0 0 0 1
footprint=none
T 67900 71900 5 8 0 0 0 0 1
symversion=1.0
T 67900 70400 5 10 0 0 0 0 1
net=3V3:1
T 68100 70400 5 10 1 1 0 0 1
value=3V3
}
C 61700 65100 1 90 0 capacitor-1.sym
{
T 61000 65300 5 10 0 0 90 0 1
device=CAPACITOR
T 61800 65800 5 10 1 1 180 0 1
refdes=C22
T 60800 65300 5 10 0 0 90 0 1
symversion=0.1
T 61600 65300 5 10 1 1 0 0 1
value=0.1u
T 61700 65100 5 10 0 1 0 0 1
footprint=0603
}
N 57700 66000 62000 66000 4
C 61000 64800 1 0 0 gnd-1.sym
N 57700 65100 61500 65100 4
N 62000 68400 60700 68400 4
N 62000 66800 60700 66800 4
C 61200 71300 1 270 0 gnd-1.sym
N 60700 66000 60700 68400 4
N 60700 50400 61700 50400 4
C 37800 56200 1 270 0 capacitor-2.sym
{
T 38500 56000 5 10 0 0 270 0 1
device=POLARIZED_CAPACITOR
T 37700 55900 5 10 1 1 0 0 1
refdes=C9
T 38700 56000 5 10 0 0 270 0 1
symversion=0.1
T 37500 55400 5 10 1 1 0 0 1
value=330u
T 37800 56200 5 10 0 1 0 0 1
footprint=tant_7x4mm
}
C 38800 56200 1 270 0 capacitor-2.sym
{
T 39500 56000 5 10 0 0 270 0 1
device=POLARIZED_CAPACITOR
T 38600 55900 5 10 1 1 0 0 1
refdes=C10
T 39700 56000 5 10 0 0 270 0 1
symversion=0.1
T 38500 55400 5 10 1 1 0 0 1
value=330u
T 38800 56200 5 10 0 1 0 0 1
footprint=tant_7x4mm
}
C 37600 56200 1 0 0 vcc.sym
{
T 37600 57900 5 8 0 0 0 0 1
footprint=none
T 37600 57700 5 8 0 0 0 0 1
symversion=1.0
T 37600 56200 5 10 0 0 0 0 1
net=3V3:1
T 37300 56200 5 10 1 1 0 0 1
value=3V3
}
C 59400 65100 1 90 0 capacitor-1.sym
{
T 58700 65300 5 10 0 0 90 0 1
device=CAPACITOR
T 59500 65800 5 10 1 1 180 0 1
refdes=C19
T 58500 65300 5 10 0 0 90 0 1
symversion=0.1
T 59300 65300 5 10 1 1 0 0 1
value=1u
T 59400 65100 5 10 0 1 0 0 1
footprint=0603
}
C 60200 65100 1 90 0 capacitor-1.sym
{
T 59500 65300 5 10 0 0 90 0 1
device=CAPACITOR
T 60300 65800 5 10 1 1 180 0 1
refdes=C20
T 59300 65300 5 10 0 0 90 0 1
symversion=0.1
T 60100 65300 5 10 1 1 0 0 1
value=0.1u
T 60200 65100 5 10 0 1 0 0 1
footprint=0603
}
C 41200 55300 1 90 0 capacitor-1.sym
{
T 40500 55500 5 10 0 0 90 0 1
device=CAPACITOR
T 41100 55900 5 10 1 1 0 0 1
refdes=C14
T 40300 55500 5 10 0 0 90 0 1
symversion=0.1
T 41100 55500 5 10 1 1 0 0 1
value=1u
T 41200 55300 5 10 0 1 0 0 1
footprint=0603
}
N 37700 56200 41000 56200 4
N 38000 55300 41000 55300 4
C 39400 55000 1 0 0 gnd-1.sym
C 37600 54100 1 0 0 vcc.sym
{
T 37600 55800 5 8 0 0 0 0 1
footprint=none
T 37600 55600 5 8 0 0 0 0 1
symversion=1.0
T 37600 54100 5 10 0 0 0 0 1
net=5V:1
T 37400 54100 5 10 1 1 0 0 1
value=5V
}
C 38000 54100 1 270 0 capacitor-2.sym
{
T 38700 53900 5 10 0 0 270 0 1
device=POLARIZED_CAPACITOR
T 37800 53800 5 10 1 1 0 0 1
refdes=C11
T 38900 53900 5 10 0 0 270 0 1
symversion=0.1
T 37700 53300 5 10 1 1 0 0 1
value=330u
T 38000 54100 5 10 0 1 0 0 1
footprint=tant_7x4mm
}
C 39300 53200 1 90 0 capacitor-1.sym
{
T 38600 53400 5 10 0 0 90 0 1
device=CAPACITOR
T 39200 53800 5 10 1 1 0 0 1
refdes=C15
T 38400 53400 5 10 0 0 90 0 1
symversion=0.1
T 39200 53400 5 10 1 1 0 0 1
value=1u
T 39300 53200 5 10 0 1 0 0 1
footprint=0603
}
C 78000 49000 1 90 0 capacitor-1.sym
{
T 77300 49200 5 10 0 0 90 0 1
device=CAPACITOR
T 77400 49600 5 10 1 1 0 0 1
refdes=C16
T 77100 49200 5 10 0 0 90 0 1
symversion=0.1
T 77500 49200 5 10 1 1 0 0 1
value=1u
T 78000 49000 5 10 0 1 0 0 1
footprint=0603
}
C 40900 53200 1 90 0 capacitor-1.sym
{
T 40200 53400 5 10 0 0 90 0 1
device=CAPACITOR
T 40800 53800 5 10 1 1 0 0 1
refdes=C17
T 40000 53400 5 10 0 0 90 0 1
symversion=0.1
T 40800 53400 5 10 1 1 0 0 1
value=1u
T 40900 53200 5 10 0 1 0 0 1
footprint=0603
}
N 37700 54100 40700 54100 4
N 38200 53200 40700 53200 4
C 40200 55300 1 90 0 capacitor-1.sym
{
T 39500 55500 5 10 0 0 90 0 1
device=CAPACITOR
T 40100 55900 5 10 1 1 0 0 1
refdes=C12
T 39300 55500 5 10 0 0 90 0 1
symversion=0.1
T 40100 55500 5 10 1 1 0 0 1
value=1u
T 40200 55300 5 10 0 1 0 0 1
footprint=0603
}
C 45400 56300 1 0 0 jumper2.sym
{
T 46400 56500 5 8 0 0 0 0 1
device=JUMPER2
T 45800 57200 5 10 1 1 0 0 1
refdes=CH1
T 46400 56300 5 8 0 0 0 0 1
footprint=JUMPER2
}
C 45400 55000 1 0 0 jumper2.sym
{
T 46400 55200 5 8 0 0 0 0 1
device=JUMPER2
T 45800 55900 5 10 1 1 0 0 1
refdes=CH2
T 46400 55000 5 8 0 0 0 0 1
footprint=JUMPER2
}
C 45400 53700 1 0 0 jumper2.sym
{
T 46400 53900 5 8 0 0 0 0 1
device=JUMPER2
T 45800 54600 5 10 1 1 0 0 1
refdes=CH3
T 46400 53700 5 8 0 0 0 0 1
footprint=JUMPER2
}
C 45400 52400 1 0 0 jumper2.sym
{
T 46400 52600 5 8 0 0 0 0 1
device=JUMPER2
T 45800 53300 5 10 1 1 0 0 1
refdes=CH4
T 46400 52400 5 8 0 0 0 0 1
footprint=JUMPER2
}
C 44600 56400 1 0 0 input-1.sym
{
T 44600 56700 5 10 0 0 0 0 1
device=INPUT
T 44600 56400 5 10 0 0 0 0 1
net=CH1:1
T 44200 56400 5 10 1 1 0 0 1
value=CH1
}
C 44600 55100 1 0 0 input-1.sym
{
T 44600 55400 5 10 0 0 0 0 1
device=INPUT
T 44600 55100 5 10 0 0 0 0 1
net=CH2:1
T 44200 55100 5 10 1 1 0 0 1
value=CH2
}
C 44600 53800 1 0 0 input-1.sym
{
T 44600 54100 5 10 0 0 0 0 1
device=INPUT
T 44600 53800 5 10 0 0 0 0 1
net=CH3:1
T 44200 53800 5 10 1 1 0 0 1
value=CH3
}
C 44600 52500 1 0 0 input-1.sym
{
T 44600 52800 5 10 0 0 0 0 1
device=INPUT
T 44600 52500 5 10 0 0 0 0 1
net=CH4:1
T 44200 52500 5 10 1 1 0 0 1
value=CH4
}
C 55200 53200 1 0 0 output-1.sym
{
T 55300 53500 5 10 0 0 0 0 1
device=OUTPUT
T 55200 53200 5 10 0 0 0 0 1
net=SS1:1
T 56000 53200 5 10 1 1 0 0 1
value=SS1
}
N 55200 53300 54800 53300 4
C 55200 50000 1 0 0 output-1.sym
{
T 55300 50300 5 10 0 0 0 0 1
device=OUTPUT
T 55200 50000 5 10 0 0 0 0 1
net=SS2:1
T 56000 50000 5 10 1 1 0 0 1
value=SS2
}
N 55200 50100 54800 50100 4
C 45900 48400 1 0 0 jumper7.sym
{
T 46900 49400 5 8 0 0 0 0 1
device=JUMPER7
T 46300 51300 5 10 1 1 0 0 1
refdes=SPI
T 46900 49200 5 8 0 0 0 0 1
footprint=JUMPER7
}
C 44700 49700 1 0 0 input-1.sym
{
T 44700 50000 5 10 0 0 0 0 1
device=INPUT
T 44700 49700 5 10 0 0 0 0 1
net=SS2:1
T 44300 49700 5 10 1 1 0 0 1
value=SS2
}
N 45500 49800 45900 49800 4
C 39400 52900 1 0 0 gnd-1.sym
C 55200 55600 1 0 0 output-1.sym
{
T 55300 55900 5 10 0 0 0 0 1
device=OUTPUT
T 55200 55600 5 10 0 0 0 0 1
net=WIFI_RESET:1
T 56000 55600 5 10 1 1 0 0 1
value=WIFI_RESET
}
N 55200 55700 54800 55700 4
C 50100 47600 1 0 0 HYSTM32.sym
{
T 54400 74800 5 10 1 1 0 6 1
refdes=U3
T 50500 76000 5 10 0 0 0 0 1
device=HYSTM32
T 50500 76200 5 10 0 0 0 0 1
footprint=HYSTM32
}
C 72100 53000 1 0 1 jumper2.sym
{
T 71100 53200 5 8 0 0 0 6 1
device=JUMPER2
T 71800 53900 5 10 1 1 0 6 1
refdes=LEDL1
T 71100 53000 5 8 0 0 0 6 1
footprint=JUMPER2
}
C 60700 50600 1 180 0 capacitor-1.sym
{
T 60500 49900 5 10 0 0 180 0 1
device=CAPACITOR
T 59800 50600 5 10 1 1 0 0 1
refdes=C27
T 60500 49700 5 10 0 0 180 0 1
symversion=0.1
T 60400 50600 5 10 1 1 0 0 1
value=1u
T 60700 50600 5 10 0 1 90 0 1
footprint=0603
}
C 59500 50500 1 270 0 gnd-1.sym
C 73700 53000 1 0 1 jumper2.sym
{
T 72700 53200 5 8 0 0 0 6 1
device=JUMPER2
T 73400 53900 5 10 1 1 0 6 1
refdes=LEDL2
T 72700 53000 5 8 0 0 0 6 1
footprint=JUMPER2
}
C 71800 54500 1 0 0 MOSFET_P-2.sym
{
T 72350 55400 5 10 1 1 0 6 1
refdes=Q1
T 72100 56650 5 10 0 0 0 0 1
device=MOSFET P-Channel
T 71800 54500 5 10 0 1 0 0 1
footprint=SOT23
}
C 72300 56100 1 0 0 vcc.sym
{
T 72300 57800 5 8 0 0 0 0 1
footprint=none
T 72300 57600 5 8 0 0 0 0 1
symversion=1.0
T 72300 56100 5 10 0 0 0 0 1
net=5V:1
T 72500 56100 5 10 1 1 0 0 1
value=5V
}
C 71800 55900 1 180 0 resistor-2.sym
{
T 71400 55550 5 10 0 0 180 0 1
device=RESISTOR
T 71000 55900 5 10 1 1 0 0 1
refdes=R25
T 71400 55900 5 10 1 1 0 0 1
value=50k
T 71800 55900 5 10 0 1 0 0 1
footprint=0603
}
N 72400 56100 72400 55400 4
C 69200 54600 1 0 0 input-1.sym
{
T 69200 54900 5 10 0 0 0 0 1
device=INPUT
T 69200 54600 5 10 0 0 0 0 1
net=LED1:1
T 68700 54600 5 10 1 1 0 0 1
value=LED1
}
N 70900 55800 70500 55800 4
N 70500 55800 70500 54700 4
N 70000 54700 71800 54700 4
N 71800 55800 72400 55800 4
C 72400 53000 1 270 0 resistor-2.sym
{
T 72750 52600 5 10 0 0 270 0 1
device=RESISTOR
T 72400 52500 5 10 1 1 180 0 1
refdes=R26
T 72400 52800 5 10 1 1 180 0 1
value=300
T 72400 53000 5 10 0 1 90 0 1
footprint=0603
}
N 72100 53600 72400 53600 4
N 72400 53600 72400 54500 4
N 72100 53200 72500 53200 4
N 72500 53200 72500 53000 4
C 72400 51800 1 0 0 gnd-1.sym
N 73700 53600 73700 54500 4
N 73700 54500 72400 54500 4
C 73600 53000 1 270 0 resistor-2.sym
{
T 73950 52600 5 10 0 0 270 0 1
device=RESISTOR
T 73600 52500 5 10 1 1 180 0 1
refdes=R28
T 73600 52800 5 10 1 1 180 0 1
value=300
T 73600 53000 5 10 0 1 90 0 1
footprint=0603
}
C 73600 51800 1 0 0 gnd-1.sym
N 73700 53000 73700 53200 4
C 72200 48100 1 0 1 jumper2.sym
{
T 71200 48300 5 8 0 0 0 6 1
device=JUMPER2
T 71900 49000 5 10 1 1 0 6 1
refdes=LEDR1
T 71200 48100 5 8 0 0 0 6 1
footprint=JUMPER2
}
C 73800 48100 1 0 1 jumper2.sym
{
T 72800 48300 5 8 0 0 0 6 1
device=JUMPER2
T 73500 49000 5 10 1 1 0 6 1
refdes=LEDR2
T 72800 48100 5 8 0 0 0 6 1
footprint=JUMPER2
}
C 71900 49600 1 0 0 MOSFET_P-2.sym
{
T 72450 50500 5 10 1 1 0 6 1
refdes=Q2
T 72200 51750 5 10 0 0 0 0 1
device=MOSFET P-Channel
T 71900 49600 5 10 0 1 0 0 1
footprint=SOT23
}
C 72400 51200 1 0 0 vcc.sym
{
T 72400 52900 5 8 0 0 0 0 1
footprint=none
T 72400 52700 5 8 0 0 0 0 1
symversion=1.0
T 72400 51200 5 10 0 0 0 0 1
net=5V:1
T 72600 51200 5 10 1 1 0 0 1
value=5V
}
C 71900 51000 1 180 0 resistor-2.sym
{
T 71500 50650 5 10 0 0 180 0 1
device=RESISTOR
T 71100 51000 5 10 1 1 0 0 1
refdes=R27
T 71500 51000 5 10 1 1 0 0 1
value=50k
T 71900 51000 5 10 0 1 0 0 1
footprint=0603
}
N 72500 51200 72500 50500 4
C 69300 49700 1 0 0 input-1.sym
{
T 69300 50000 5 10 0 0 0 0 1
device=INPUT
T 69300 49700 5 10 0 0 0 0 1
net=LED2:1
T 68800 49700 5 10 1 1 0 0 1
value=LED2
}
N 71000 50900 70600 50900 4
N 70600 50900 70600 49800 4
N 70100 49800 71900 49800 4
N 71900 50900 72500 50900 4
C 72500 48100 1 270 0 resistor-2.sym
{
T 72850 47700 5 10 0 0 270 0 1
device=RESISTOR
T 72500 47600 5 10 1 1 180 0 1
refdes=R29
T 72500 47900 5 10 1 1 180 0 1
value=300
T 72500 48100 5 10 0 1 90 0 1
footprint=0603
}
N 72200 48700 72500 48700 4
N 72500 48700 72500 49600 4
N 72200 48300 72600 48300 4
N 72600 48300 72600 48100 4
C 72500 46900 1 0 0 gnd-1.sym
N 73800 48700 73800 49600 4
N 73800 49600 72500 49600 4
C 73700 48100 1 270 0 resistor-2.sym
{
T 74050 47700 5 10 0 0 270 0 1
device=RESISTOR
T 73700 47600 5 10 1 1 180 0 1
refdes=R30
T 73700 47900 5 10 1 1 180 0 1
value=300
T 73700 48100 5 10 0 1 90 0 1
footprint=0603
}
C 73700 46900 1 0 0 gnd-1.sym
N 73800 48100 73800 48300 4
C 77200 49900 1 0 0 MOSFET_P-2.sym
{
T 77750 50800 5 10 1 1 0 6 1
refdes=Q3
T 77500 52050 5 10 0 0 0 0 1
device=MOSFET P-Channel
T 77200 49900 5 10 0 1 0 0 1
footprint=SOT23
}
C 77700 51500 1 0 0 vcc.sym
{
T 77700 53200 5 8 0 0 0 0 1
footprint=none
T 77700 53000 5 8 0 0 0 0 1
symversion=1.0
T 77700 51500 5 10 0 0 0 0 1
net=5V:1
T 77900 51500 5 10 1 1 0 0 1
value=5V
}
C 77200 51300 1 180 0 resistor-2.sym
{
T 76800 50950 5 10 0 0 180 0 1
device=RESISTOR
T 76400 51300 5 10 1 1 0 0 1
refdes=R31
T 76800 51300 5 10 1 1 0 0 1
value=50k
T 77200 51300 5 10 0 1 0 0 1
footprint=0603
}
N 77800 51500 77800 50800 4
C 74600 50000 1 0 0 input-1.sym
{
T 74600 50300 5 10 0 0 0 0 1
device=INPUT
T 74600 50000 5 10 0 0 0 0 1
net=VCCGSP:1
T 74100 50300 5 10 1 1 0 0 1
value=VCCGSP
}
N 76300 51200 75900 51200 4
N 75900 51200 75900 50100 4
N 75400 50100 77200 50100 4
N 77200 51200 77800 51200 4
C 77700 48700 1 0 0 gnd-1.sym
N 55200 50900 54800 50900 4
C 49000 72700 1 0 0 schottky-1.sym
{
T 49322 73372 5 10 0 0 0 0 1
device=10MQ060N
T 49300 73200 5 10 1 1 0 0 1
refdes=D9
T 49341 73532 5 10 0 1 0 0 1
footprint=10MQ060N
}
N 49900 72900 50200 72900 4
N 48600 72900 49000 72900 4
C 57900 65100 1 90 0 capacitor-1.sym
{
T 57200 65300 5 10 0 0 90 0 1
device=CAPACITOR
T 57000 65300 5 10 0 0 90 0 1
symversion=0.1
T 57900 65100 5 10 0 1 0 0 1
footprint=0603
T 58000 65800 5 10 1 1 180 0 1
refdes=C28
T 57800 65300 5 10 1 1 0 0 1
value=1u
}
C 58700 65100 1 90 0 capacitor-1.sym
{
T 58000 65300 5 10 0 0 90 0 1
device=CAPACITOR
T 57800 65300 5 10 0 0 90 0 1
symversion=0.1
T 58700 65100 5 10 0 1 0 0 1
footprint=0603
T 58800 65800 5 10 1 1 180 0 1
refdes=C29
T 58600 65300 5 10 1 1 0 0 1
value=0.1u
}