Commits included in published releases. Unpublished intermediate commits are private. Showing matches from the latest 100 commits ending at this release.
Merge pull request #25 from open-sdr/dot11zynq
Jinghao Shi · Jan 29, 2023, 5:08 AM UTC
ea638eb2d3ab
Merge pull request #6 from ytakeuch/dot11zynq
Jiao Xianjun · Jan 28, 2023, 11:00 AM UTC
19acdbe82f96
Merge pull request #7 from open-sdr/pre-release
Jiao Xianjun · Jan 28, 2023, 10:56 AM UTC
583753829d37
Add neptunesdr to related files
Xianjun Jiao · Jan 16, 2023, 12:40 PM UTC
36c6b0f59a62
fix unsigned signals to signed signals
Yoji Takeuchi · Jan 16, 2023, 3:56 AM UTC
7e8b44439ab0
Add antsdr/e200 and sdrpi
Xianjun Jiao · Jan 9, 2023, 3:00 PM UTC
3f645e30f464
Change the phase control value to the most safe one
Xianjun Jiao · Jan 9, 2023, 2:57 PM UTC
8aa784707ac5
Add precise sample_in_strobe phase control into dot11_tb.v for debugging the back luck FPGA loopback issue
Xianjun Jiao · Jan 9, 2023, 2:56 PM UTC
b2e08ff46e3b
Fix the ofdm_symbol_eq_out_pulse according to the new euqalizer states
Xianjun Jiao · Jan 9, 2023, 2:55 PM UTC
db87c8d8a9c0
Add centralized DBG switch
Xianjun Jiao · Jan 9, 2023, 2:54 PM UTC
b7ba58b60a00
Update script for vivado 2021.1
Xianjun Jiao · Jan 9, 2023, 2:50 PM UTC
ec2a5e8105f9
Add DEBUG but not enabled
Xianjun Jiao · Jan 9, 2023, 2:49 PM UTC
f59c9418a7ba
Remove floating connections
Xianjun Jiao · Jan 9, 2023, 2:48 PM UTC
ad5a5206d35f
LVPE correction before estimation - Add state in equalizer and rename others - Add new dumper files in testbench to check with MATLAB
thavinga · Jan 9, 2023, 2:45 PM UTC
95e93cadfd4e
Add FFT window shift register
thavinga · Jan 9, 2023, 2:40 PM UTC
b0df85040f85
Avoid phy_len_calculation out of the watchdog reset scope to have stable value before the next long_preamble_detected
Xianjun Jiao · Jan 9, 2023, 2:33 PM UTC
1b0354f85db1
Enable threshold scale for receiver and disable power trigger for watchdog by default
Xianjun Jiao · Jan 9, 2023, 2:32 PM UTC
e83599a85e1f
signal watchdog only work while rssi above threshold: power_trigger valid
Xianjun Jiao · Jan 9, 2023, 2:31 PM UTC
104342976290
Make minimum pkt length configurable for signal_watchdog
Xianjun Jiao · Jan 9, 2023, 2:30 PM UTC
54bdff734859
Add fake random +/-1 input while input are 0s: to avoid receiver reset during self-rx-muting (packet sending)
Xianjun Jiao · Jan 9, 2023, 2:29 PM UTC
75979e165a70
Add phy len indication for decoding latency prediciton: Add n_ofdm_sym, n_bit_in_last_sym and phy_len_valid to openofdm_rx ip
Xianjun Jiao · Jan 9, 2023, 2:28 PM UTC
73475306b7c8
Add phy len log into dot11_tb
Xianjun Jiao · Jan 9, 2023, 2:25 PM UTC
4359e4f96d1d
Shrink the bits of num_bits_to_decode and deinter_out_count: and adapt the verilog/ofdm_decoder.v accordingly
Xianjun Jiao · Jan 9, 2023, 2:24 PM UTC
8ce830c262e6
Adapt CPE/LVPE calculation
thavinga · Jan 9, 2023, 2:20 PM UTC
efa844bf0c8e
Adapt the test bench to align with ...
Xianjun Jiao · Jan 9, 2023, 1:51 PM UTC
27392f217fef
Resolve the cpe/lvpe overflow issue
Xianjun Jiao · Jan 9, 2023, 1:51 PM UTC
e978f30de668
Feed data to ofdm decoder earlier in case a data is missed (arrive too early for ofdm decoder)
Xianjun Jiao · Jan 9, 2023, 1:50 PM UTC
f455472288a6
Reset internally equalizer after it is disabled to prepare for next round enable
Xianjun Jiao · Jan 9, 2023, 1:49 PM UTC
71c9b42d7869
Let sync short restart earlier before the end of current packet decoding, so that the next packet can come earlier (smaller inter packet gap is achieved)
Xianjun Jiao · Jan 9, 2023, 1:48 PM UTC
8e59685c6510
Make some basic block simpler and its delay more deterministic
Xianjun Jiao · Jan 9, 2023, 1:47 PM UTC
e65ee43101f0
Add threshold_scale and enable it by default: sync short works at low SNR and the receiver sensitivity is better
Xianjun Jiao · Jan 9, 2023, 1:43 PM UTC
a1e1e0090b3a
extend the status_code to more formated style
Xianjun Jiao · Jan 9, 2023, 1:40 PM UTC
6a8818fe5fa2
fix viterbi decoder logging issue
Wei Liu · Jan 5, 2023, 3:47 PM UTC
2747d431f9b9
log all header bits, also when error occors
Wei Liu · Jan 5, 2023, 3:45 PM UTC
fe93170efc78
clean up log file, prolong simulation at the end by 300 sp
Wei Liu · Jan 5, 2023, 3:38 PM UTC
c9f3d280a357
add support for antsdr e200
black_pigeon · Oct 21, 2022, 4:58 PM UTC
f3bf82a05bf5
Add neptunesdr
Xianjun Jiao · Oct 16, 2022, 8:09 PM UTC
3d0a40958cb3
Merge pull request #24 from redfast00/fix-reserved-ht-header
Jinghao Shi · Aug 18, 2022, 6:47 AM UTC
0c2c2d7f7613
Fix reserved bit in SIG-HT header
redfast00 · Aug 18, 2022, 6:13 AM UTC
a77a1abd016b
Update parse_board_name.tcl
HexSDR · Aug 5, 2022, 3:49 PM UTC
76986e99d316
Update create_vivado_proj.sh
HexSDR · Aug 5, 2022, 3:49 PM UTC
8a74580ad1b4
Remove the huge logging thing in dot11_tb.v
Xianjun Jiao · Jul 15, 2022, 10:10 AM UTC
707cb99a9093
Merge pull request #21 from jhshi/dependabot/pip/numpy-1.22.0
Jinghao Shi · Jun 22, 2022, 12:34 AM UTC
864096ac05f0
Bump numpy from 1.11.2 to 1.22.0
dependabot[bot] · Jun 21, 2022, 9:12 PM UTC
f6679c7f1879
Auto stop the simulation at the end of iq sample file
Xianjun Jiao · May 16, 2022, 7:53 AM UTC
064bbe425067
Minor cleaning
Xianjun Jiao · May 16, 2022, 7:52 AM UTC
f6fd0a2a85e1
Disable signal watch dog for normal simulation in the tb
Xianjun Jiao · May 16, 2022, 7:51 AM UTC
7622d7aaa09d
Connect pkt_len from dot11 to signal watch dog in the tb
Xianjun Jiao · May 16, 2022, 7:51 AM UTC
55f77bb16ba4
Move all signal logging to dot11_tb.v
thavinga · May 16, 2022, 7:33 AM UTC
cb6b566d5f9a
Add conditional compiling framework
Xianjun Jiao · May 13, 2022, 11:24 AM UTC
1659c01ac7f6
Workaround to supress the error message when the 1st time run simulation
Xianjun Jiao · May 13, 2022, 11:21 AM UTC
a7b95b492c7b
Change the device/board to 7020 for low-end device friendly (Avoid the license issue in the default case)
Jiao Xianjun · May 11, 2022, 8:30 AM UTC
ac1a75e55a0a
Merge pull request #19 from open-sdr/dot11zynq
Jinghao Shi · Apr 1, 2022, 10:48 PM UTC
0ab83ce22385
Merge pull request #1 from open-sdr/pre-release
Jiao Xianjun · Apr 1, 2022, 9:07 AM UTC
5d4e72f66e2c
Add slv_reg1[4] for option of disabling all smoothing
Xianjun Jiao · Mar 29, 2022, 10:50 AM UTC
4168aa8c7a7d
Fix the issue of adrv9364z7020: demod_is_ongoing always high. dot11 stuck at state 3 Seems new viter decoder IP core does not need this complicated CE signal vit_ce in ofdm_decoder.v Setting the vit-ce to always 1 fixed the issue
Xianjun Jiao · Mar 23, 2022, 1:26 PM UTC
39911461ef93
Add more test vectors into testing_inputs/simulated
Xianjun Jiao · Mar 16, 2022, 2:07 PM UTC
44c8846072f2
Add signal_watchdog module to prevent fake demod in early phase: 1. If strong DC or low frequency sing wave like signal (suspect it is generated by ad9361 during some self-calibration like operation), put the receiver into reset 2. If the signal/header is valid, but the packet length is abnormal (signal_len<14 || signal_len>max_signal_len_th), reset the receiver
Xianjun Jiao · Mar 15, 2022, 3:03 PM UTC
f08c76ca3d63
Add git rev tracking to reg 31
Xianjun Jiao · Mar 15, 2022, 2:57 PM UTC
e77f1ba70bde
Add a test vector fake-demod-0.txt that could cause fake demodulation
Xianjun Jiao · Mar 15, 2022, 2:53 PM UTC
954bae4e7751
remove unnecessary atan_lut files
Xianjun Jiao · Mar 15, 2022, 2:52 PM UTC
40b3e59958dc
Merge pull request #18 from open-sdr/dot11zynq
Jinghao Shi · Jan 28, 2022, 7:11 PM UTC
4ad09c44c31d
Add more clock cases into dot11_tb.v
Xianjun Jiao · Jan 28, 2022, 11:17 AM UTC
566e82f43edb
Add force ht smoothing option: > 1. Leave the module always enabled, so the slv_reg1 is free > 2. Use the slv_reg1 to force ht smoothing > 3. By default, the smoothing option of the receiver is still controlled by the received ht packet
Xianjun Jiao · Jan 28, 2022, 11:15 AM UTC
030cdb34ca84
Avoid equalizer module processing HT_STF symbol
mmehari · Jan 4, 2022, 9:45 PM UTC
23e61e6a29f8
bug fix: remaining packet length calculation
mmehari · Jan 4, 2022, 9:44 PM UTC
0c75a8e8f295
feature update: sampling frequency offset (SFO) compensation
mmehari · Jan 4, 2022, 9:26 PM UTC
8730912d6f2c
Advance phase correction value by guard interval size
mmehari · Jan 4, 2022, 9:25 PM UTC
b40c221e6711
bug fix: increase phase calculation delay by 1 CLK
mmehari · Jan 4, 2022, 9:22 PM UTC
85b1adbec737
storage update: A-MPDU decoding
mmehari · Jan 4, 2022, 9:20 PM UTC
e257d3373bac
Save channel gain information of HT-LTF
mmehari · Jan 4, 2022, 9:19 PM UTC
af855d8c10a4
provide demod_soft_bits and demod_soft_bits_pos signals out
mmehari · Jan 4, 2022, 9:18 PM UTC
48aade019092
Don't catagorize IQ modulation as Q-BPSK or BPSK when I and Q components have the same magnitude
integer division rounding fix during phase offset calculation
mmehari · Jan 4, 2022, 9:12 PM UTC
53679a107f62
keep significant bits while performing division during phase calculation
mmehari · Jan 4, 2022, 9:11 PM UTC
82d2d456e526
phase register size reduction: 32bit -> 16bit
mmehari · Jan 4, 2022, 9:10 PM UTC
d9649eb6141a
long preamble detection method update: cross-correlation inter-peak gap distance -> 1st peak detection
mmehari · Jan 4, 2022, 9:07 PM UTC
f3e95eaa92b6
HT/non_HT detection requires at most 9 clocks
mmehari · Jan 4, 2022, 9:05 PM UTC
aaa8ef3ce527
channel smoothing update based on HT-SIG field
mmehari · Jan 4, 2022, 9:03 PM UTC
8bc2d7f0a43b
A-MPDU decoding support
mmehari · Jan 4, 2022, 9:01 PM UTC
171ef8b27a02
Provide ht_aggregation signal out
mmehari · Jan 4, 2022, 9:00 PM UTC
1a9246fd24ea
Merge pull request #15 from open-sdr/dot11zynq
Jinghao Shi · Jan 8, 2021, 6:37 PM UTC
c3035cf98591
Provide ht_sgi signal out
mmehari · Nov 6, 2020, 12:20 PM UTC
f83d179cbe04
Merge pull request #14 from open-sdr/dot11zynq
Jinghao Shi · Oct 19, 2020, 9:01 AM UTC
d0f271bdc8ab
add necessary port as trigger for iq capture feature in openwifi
Xianjun Jiao · Oct 19, 2020, 7:22 AM UTC
d331e66a31b0
Merge pull request #13 from f380cedric/patch-1
Jinghao Shi · Oct 12, 2020, 5:34 PM UTC
2c57c0a096bb
Typo
f380cedric · Oct 12, 2020, 1:52 PM UTC
a7efc6cb9786
Merge pull request #12 from open-sdr/dot11zynq
Jinghao Shi · Oct 8, 2020, 9:17 AM UTC
fb5fa6a74446
output information for openwifi side channel feature: capture timestamp, frequency offset, channel state information and equalizer constellation to Linux
Xianjun Jiao · Oct 8, 2020, 8:06 AM UTC
8714c30857ea
Merge pull request #11 from open-sdr/dot11zynq
Jinghao Shi · Sep 4, 2020, 6:49 AM UTC
229da948ae4d
make the code more testbench friendly
Xianjun Jiao · Sep 2, 2020, 7:59 PM UTC
539133f453bd
turn on soft_decoding in dot11_tb.v
Xianjun Jiao · Sep 2, 2020, 3:15 PM UTC
2b3a043e8cf2
fix the project_name and script_file in openofdm_rx_ultra_scale.tcl
Xianjun Jiao · Sep 2, 2020, 3:05 PM UTC
6d60fceed265
change the latency of divider from automatic 60 clocks to the original 36 clock
Xianjun Jiao · Sep 2, 2020, 2:49 PM UTC
bf043af712aa
802.11n rx performance fix when used different clock rates (i.e. 100MHz vs 200MHz)
mmehari · Aug 30, 2020, 1:23 PM UTC
b86951097c65
fix the atan_addr overflow issue (phase.v)
Xianjun Jiao · Aug 29, 2020, 12:48 PM UTC
d7f5806790ab
channel estimation update: frequency domain averaging