motorcontroller-hw

EESchema-LIBRARY Version 2.3
#encoding utf-8
#
# STM32F405R-RESCUE-bldc-controller
#
DEF STM32F405R-RESCUE-bldc-controller U 0 40 Y Y 1 F N
F0 "U" 100 -550 50 H V C CNN
F1 "STM32F405R-RESCUE-bldc-controller" 100 -450 50 H V C CNN
F2 "TQFP64" 100 -650 50 H V C CNN
F3 "" 100 -550 50 H V C CNN
$FPLIST
 LQFP64
$ENDFPLIST
DRAW
S -3300 -2100 3100 2000 0 1 0 f
X VBAT 1 1000 2300 300 D 50 50 1 1 I
X PC13 2 3400 -1500 300 L 50 50 1 1 I
X PC14/OSC32_IN 3 3400 -1600 300 L 50 50 1 1 I
X PC15/OSC32_OUT 4 3400 -1700 300 L 50 50 1 1 I
X PH0/OSC_IN 5 -3600 1100 300 R 50 50 1 1 I
X PH1/OSC_OUT 6 -3600 500 300 R 50 50 1 1 O
X NRST 7 -3600 1300 300 R 50 50 1 1 B
X PC0/OTG_HS_ULPI_STP 8 3400 -200 300 L 50 50 1 1 I
X PC1 9 3400 -300 300 L 50 50 1 1 I
X PC2/SPI2_MISO/OTG_HS_ULPI_DIR/I2S2ext_SD 10 3400 -400 300 L 50 50 1 1 I
X PA4/SPI1_NSS/SPI3_NSS/USART2_CK/OTG_HS_SOF/I2S3_WS 20 -3600 -700 300 R 50 50 1 1 I
X PB11/I2C2_SDA/USART3_RX/OTG_HS_ULPI_D4/TIM2_CH4 30 3400 500 300 L 50 50 1 1 I
X PC9/I2S_CKIN/MCO2/TIM8_CH4/SDIO_D1/I2C3_SDA/TIM3_CH4 40 3400 -1100 300 L 50 50 1 1 I
X PA15/JTDI/SPI3_NSS/I2S3_WS/TIM2_CH1_ETR/SPI1_NSS 50 -3600 -1800 300 R 50 50 1 1 I
X BOOT0 60 -3600 1500 300 R 50 50 1 1 I
X PC3/SPI2_MOSI/I2S2_SD/OTG_HS_ULPI_NXT 11 3400 -500 300 L 50 50 1 1 I
X PA5/SPI1_SCK/OTG_HS_ULPI_CK/TIM2_CH1_ETR/TIM8_CHIN 21 -3600 -800 300 R 50 50 1 1 I
X VCAP_1 31 300 -2400 300 U 50 50 1 1 I
X PA8/MCO1/USART1_CK/TIM1_CH1/I2C3_SCL/OTG_FS_SOF 41 -3600 -1100 300 R 50 50 1 1 I
X PC10/SPI3_SCK/I2S3_CK/UART4_TX/SDIO_D2/USART3_TX 51 3400 -1200 300 L 50 50 1 1 I
X PB8/TIM4_CH3/SDIO_D4/TIM10_CH1/I2C1_SCL/CAN1_RX 61 3400 800 300 L 50 50 1 1 I
X VSSA 12 -1000 -2400 300 U 50 50 1 1 I
X PA6/SPI1_MISO/TIM8_BKIN/TIM13_CH1/TIM3_CH1/TIM1_BKIN 22 -3600 -900 300 R 50 50 1 1 I
X VDD 32 -100 2300 300 D 50 50 1 1 I
X PA9/USART1_TX/TIM1_CH2/I2C3_SMBA 42 -3600 -1200 300 R 50 50 1 1 I
X PC11/UART4_RX/SPI3_MISO/SDIO_D3/USART3_RX/I2S3ext_SD 52 3400 -1300 300 L 50 50 1 1 I
X PB9/SPI2_NSS/I2S2_WS/TIM4_CH4/TIM11_CH1/SDIO_D5/I2C1_SDA/CAN1_TX 62 3400 700 300 L 50 50 1 1 I
X VDDA 13 -900 2300 300 D 50 50 1 1 I
X PA7/SPI1_MOSI/TIM8_CH1N/TIM14_CH1/TIM3_CH2/TIM1_CH1N 23 -3600 -1000 300 R 50 50 1 1 I
X PB12/SPI2_NSS/I2S2_WS/I2C2_SMBA/USART3_CK/TIM1_BKIN/CAN2_RX/OTG_HS_ULPI_D5/OTG_HS_ID 33 3400 400 300 L 50 50 1 1 I
X PA10/USART1_RX/TIM1_CH3/OTG_FS_ID 43 -3600 -1300 300 R 50 50 1 1 I
X PC12/UART5_TX/SDIO_CK/SPI3_MOSI/I2S3_SD/USART3_CK 53 3400 -1400 300 L 50 50 1 1 I
X VSS 63 -600 -2400 300 U 50 50 1 1 I
X PA0/WKUP/USART2_CTS/UART4_TX/TIM2_CH1_ETR/TIM5_CH1/TIM8_ETR 14 -3600 -300 300 R 50 50 1 1 B
X PC4 24 3400 -600 300 L 50 50 1 1 I
X PB13/SPI2_SCK/I2S2_CK/USART3_CTS/TIM1_CH1N/CAN2_TX/OTG_HS_ULPI_D6 34 3400 300 300 L 50 50 1 1 I
X PA11/USART1_CTS/CAN1_RX/TIM1_CH4_/OTG_FS_DM 44 -3600 -1400 300 R 50 50 1 1 I
X PD2/TIM3_ETR/UART5_RX/SDIO_CMD 54 -3600 100 300 R 50 50 1 1 B
X VDD 64 500 2300 300 D 50 50 1 1 I
X PA1/USART2_RTS/UART4_RX/TIM5_CH2/TIMM2_CH2 15 -3600 -400 300 R 50 50 1 1 B
X PC5 25 3400 -700 300 L 50 50 1 1 I
X PB14/SPI2_MISO/TIM1_CH2N/TIM12_CH1/OTG_HS_DM/USART3_RTS/TIM8_CH2N/I2S2ext_SD 35 3400 200 300 L 50 50 1 1 I
X PA12/USART1_RTS/CAN1_TX/TIM1_ETR/OTG_FS_DP 45 -3600 -1500 300 R 50 50 1 1 I
X PB3/JTDO/TRACESWO/SPI3_SCK/I2S3_CK/TIM2_CH2/SPI1_SCK 55 3400 1300 300 L 50 50 1 1 I
X PA2/USART2_TX/TIM5_CH3/TIM9_CH1/TIM2_CH3 16 -3600 -500 300 R 50 50 1 1 I
X PB0/TIM3_CH3/TIM8_CH2N/OTG_HS_ULPI_D1/TIM1_CH2N 26 3400 1600 300 L 50 50 1 1 I
X PB15/SPI2_MOSI/I2S2_SD/TIM1_CH3N/TIM8_CH3N/TIM12_CH2/OTG_HS_DP 36 3400 100 300 L 50 50 1 1 I
X PA13/JTMS/SWDIO 46 -3600 -1600 300 R 50 50 1 1 I
X PB4/NJTRST/SPI3_MISO/TIM3_CH1/SPI1_MISO/I2S3ext_SD 56 3400 1200 300 L 50 50 1 1 I
X PA3/USART2_RX/TIM5_CH4/TIM9_CH2/TIM2_CH4/OTG_HS_ULPI_D0 17 -3600 -600 300 R 50 50 1 1 B
X PB1/TIM3_CH4/TIM8_CH3N/OTG_HS_ULPI_D2/OTG_HS_INTN/TIM1_CH3N 27 3400 1500 300 L 50 50 1 1 I
X PC6/I2S2_MCK/TIM8_CH1/SDIO_D6/USART6_TX/TIM3_CH1 37 3400 -800 300 L 50 50 1 1 I
X VCAP_2 47 800 -2400 300 U 50 50 1 1 I
X PB5/I2C1_SMBA/CAN2_RX/OTG_HS_ULPI_D7/TIM3_CH2/SPI1_MOSI/SPI3_MOSI/I2S3_SD 57 3400 1100 300 L 50 50 1 1 I
X VSS 18 -800 -2400 300 U 50 50 1 1 I
X PB2/BOOT1 28 3400 1400 300 L 50 50 1 1 I
X PC7/I2S3_MCK/TIM8_CH2/SDIO_D7/USART6_RX/TIM3_CH2 38 3400 -900 300 L 50 50 1 1 I
X VDD 48 200 2300 300 D 50 50 1 1 I
X PB6/I2C1_SCL/TIM4_CH1/CAN2_TX/USART1_TX 58 3400 1000 300 L 50 50 1 1 I
X VDD 19 -400 2300 300 D 50 50 1 1 I
X PB10/SPI2_SCK/I2S2_CK/I2C2_SCL/USART3_TX/OTG_HS_ULPI_D3/TIM2_CH3 29 3400 600 300 L 50 50 1 1 I
X PC8/TIM8_CH3/SDIO_D0/TIM3_CH3/USART6_CK 39 3400 -1000 300 L 50 50 1 1 I
X PA14/JTCK/SWCLK 49 -3600 -1700 300 R 50 50 1 1 I
X PB7/I2C1_SDA/FSMC_NL/USART1_RX/TIM4_CH2 59 3400 900 300 L 50 50 1 1 I
ENDDRAW
ENDDEF
#
#End Library