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lowrisc-chip

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Design files

Name	Storage	Size
.. / Parent directory
AsyncResetReg.v	Git	1.0 KB
ClockDivider2.v	Git	654 B
ClockDivider3.v	Git	838 B
DebugTransportJTAG-orig.sv

Dr Jonathan KimmittCorrect project file list to reflect fstore2.v -> .sv5d594a8c6

Name	Storage	Size
.. / Parent directory
AsyncResetReg.v	Git	1.0 KB
ClockDivider2.v	Git	654 B
ClockDivider3.v	Git	838 B
DebugTransportJTAG-orig.sv	Git	25.6 KB
jtag_addr.v	Git	764 B
jtag_dummy.v	Git	3.3 KB
jtag_modules.sv	Git	63.3 KB
jtag_rom.v	Git	1.7 KB
jtag_vpi.tab	Git	110 B
jtag_vpi.v	Git	6.8 KB
JTAGDTM.sv	Git	59.7 KB
JTAGDummy.v	Git	2.1 KB
jtagsm_dummy.sv	Git	4.6 KB
JtagTapController_artix.sv	Git	5.0 KB
JtagTapController_asic.sv	Git	4.6 KB
plusarg_reader.v	Git	556 B
SimDTM_JTAG.sv	Git	2.4 KB
SimDTM.v	Git	2.0 KB
TestDriver.v	Git	3.3 KB
vsim_bscan_dummy.v	Git	732 B
vsim_glbl.v	Git	4.6 KB