Loading files
This file is pinned to the selected release. Download the original to open it in your design tool.
# Copyright 2023 Efabless Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
RAW_SKY130A_IN = {
"PDK_ROOT": "/pdk_root",
"PDK": "sky130A",
"CTS_TECH_DIR": "N/A",
"FP_PDN_HOFFSET": "16.65",
"GPIO_PADS_VERILOG": " /pdk_root/sky130A/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v\n",
"STD_CELL_POWER_PINS": "VPWR VPB",
"CELLS_LEF_OPT": "/pdk_root/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_ef_sc_hd.lef /pdk_root/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef",
"FP_IO_VLAYER": "met2",
"MAGIC_TECH_FILE": "/pdk_root/sky130A/libs.tech/magic/sky130A.tech",
"FP_PDN_VERTICAL_LAYER": "met4",
"GRT_LAYER_ADJUSTMENTS": "0.99,0,0,0,0,0",
"FP_PDN_CORE_RING_VWIDTH": "1.6",
"FP_PDN_HSPACING": "1.7",
"FP_PDN_VOFFSET": "16.32",
"TECH_LEF_MAX": "/pdk_root/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__max.tlef",
"KLAYOUT_DEF_LAYER_MAP": "/pdk_root/sky130A/libs.tech/klayout/tech/sky130A.map",
"MAGIC_MAGICRC": "/pdk_root/sky130A/libs.tech/magic/sky130A.magicrc",
"FULL_ADDER_MAP": "/pdk_root/sky130A/libs.tech/openlane/sky130_fd_sc_hd/fa_map.v",
"CTS_SQR_RES": "0.125",
"RT_MAX_LAYER": "met5",
"STD_CELL_LIBRARY_OPT_CDL": "/pdk_root/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl",
"VDD_PIN": "VPWR",
"KLAYOUT_XOR_IGNORE_LAYERS": "81/14",
"RCX_RULES_MAX": "/pdk_root/sky130A/libs.tech/openlane/rules.openrcx.sky130A.max.calibre",
"TECH_LEF_OPT": "/pdk_root/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef",
"LIB_SLOWEST_OPT": "/pdk_root/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib",
"CTS_SQR_CAP": "0.258e-3",
"GDS_FILES_OPT": "/pdk_root/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds",
"FP_PDN_HWIDTH": "1.6",
"STD_CELL_GROUND_PINS": "VGND VNB",
"TRACKS_INFO_FILE": "/pdk_root/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tracks.info",
"TECH_LEF": "/pdk_root/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef",
"TECH_LEF_MIN": "/pdk_root/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__min.tlef",
"FP_PDN_HPITCH": "153.18",
"RCX_RULES": "/pdk_root/sky130A/libs.tech/openlane/rules.openrcx.sky130A.nom.calibre",
"GPIO_PADS_PREFIX": "sky130_fd_io sky130_ef_io",
"STD_CELL_LIBRARY": "sky130_fd_sc_hd",
"FP_PDN_CORE_RING_VSPACING": "1.7",
"KLAYOUT_PROPERTIES": "/pdk_root/sky130A/libs.tech/klayout/tech/sky130A.lyp",
"DRC_EXCLUDE_CELL_LIST": "/pdk_root/sky130A/libs.tech/openlane/sky130_fd_sc_hd/drc_exclude.cells",
"CARRY_SELECT_ADDER_MAP": "/pdk_root/sky130A/libs.tech/openlane/sky130_fd_sc_hd/csa_map.v",
"NO_SYNTH_CELL_LIST": "/pdk_root/sky130A/libs.tech/openlane/sky130_fd_sc_hd/no_synth.cells",
"GPIO_PADS_LEF": " /pdk_root/sky130A/libs.ref/sky130_fd_io/lef/sky130_fd_io.lef /pdk_root/sky130A/libs.ref/sky130_fd_io/lef/sky130_ef_io.lef ",
"RIPPLE_CARRY_ADDER_MAP": "/pdk_root/sky130A/libs.tech/openlane/sky130_fd_sc_hd/rca_map.v",
"CVC_SCRIPTS_DIR": "/pdk_root/sky130A/libs.tech/openlane/cvc",
"CLOCK_WIRE_RC_LAYER": "met5",
"RCX_RULES_MIN": "/pdk_root/sky130A/libs.tech/openlane/rules.openrcx.sky130A.min.calibre",
"FP_TAPCELL_DIST": "13",
"SYNTH_LATCH_MAP": "/pdk_root/sky130A/libs.tech/openlane/sky130_fd_sc_hd/latch_map.v",
"FP_PDN_VWIDTH": "1.6",
"MACRO_BLOCKAGES_LAYER": "li1 met1 met2 met3 met4",
"STD_CELL_LIBRARY_CDL": "/pdk_root/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl",
"RT_MIN_LAYER": "met1",
"VDD_PIN_VOLTAGE": "1.80",
"FP_PDN_VPITCH": "153.6",
"DRC_EXCLUDE_CELL_LIST_OPT": "/pdk_root/sky130A/libs.tech/openlane/sky130_fd_sc_hd/drc_exclude.cells",
"GDS_FILES": "/pdk_root/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds",
"FP_PDN_RAIL_LAYER": "met1",
"FP_PDN_HORIZONTAL_LAYER": "met5",
"KLAYOUT_TECH": "/pdk_root/sky130A/libs.tech/klayout/tech/sky130A.lyt",
"FP_PDN_CORE_RING_HOFFSET": "6",
"NETGEN_SETUP_FILE": "/pdk_root/sky130A/libs.tech/netgen/sky130A_setup.tcl",
"KLAYOUT_DRC_TECH_SCRIPT": "/pdk_root/sky130A/libs.tech/klayout/drc/sky130A_mr.drc",
"FP_PDN_VSPACING": "1.7",
"GND_PIN": "VGND",
"CELLS_LEF": "/pdk_root/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_ef_sc_hd.lef /pdk_root/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef",
"TRISTATE_BUFFER_MAP": "/pdk_root/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tribuff_map.v",
"FP_PDN_RAIL_OFFSET": "0",
"GPIO_PADS_LEF_CORE_SIDE": " /pdk_root/sky130A/libs.tech/openlane/custom_cells/lef/sky130_fd_io_core.lef /pdk_root/sky130A/libs.tech/openlane/custom_cells/lef/sky130_ef_io_core.lef ",
"FP_IO_HLAYER": "met3",
"FP_PDN_CORE_RING_HSPACING": "1.7",
"STD_CELL_LIBRARY_OPT": "sky130_fd_sc_hd",
"GND_PIN_VOLTAGE": "0.00",
"FP_PDN_CORE_RING_HWIDTH": "1.6",
"DEF_UNITS_PER_MICRON": "1000",
"DATA_WIRE_RC_LAYER": "met2",
"FP_PDN_CORE_RING_VOFFSET": "6",
"PROCESS": "130",
"PL_LIB": "/pdk_root/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib",
"CELL_PAD_EXCLUDE": "sky130_fd_sc_hd__tap* sky130_fd_sc_hd__decap* sky130_ef_sc_hd__decap* sky130_fd_sc_hd__fill*",
"SYNTH_MIN_BUF_PORT": "sky130_fd_sc_hd__buf_2 A X",
"DIODE_CELL": "sky130_fd_sc_hd__diode_2",
"LIB_SYNTH": "/pdk_root/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib",
"CLK_BUFFER_INPUT": "A",
"SYNTH_TIELO_PORT": "sky130_fd_sc_hd__conb_1 LO",
"FP_PDN_RAIL_WIDTH": "0.48",
"FP_WELLTAP_CELL": "sky130_fd_sc_hd__tapvpwrvgnd_1",
"SYNTH_MUX4_MAP": "/pdk_root/sky130A/libs.tech/openlane/sky130_fd_sc_hd/mux4_map.v",
"LIB_TYPICAL": "/pdk_root/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib",
"FILL_CELL": "sky130_fd_sc_hd__fill*",
"LIB_SLOWEST": "/pdk_root/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib",
"DPL_CELL_PADDING": "0",
"DIODE_CELL_PIN": "DIODE",
"SYNTH_MUX_MAP": "/pdk_root/sky130A/libs.tech/openlane/sky130_fd_sc_hd/mux2_map.v",
"CTS_CLK_BUFFER_LIST": "sky130_fd_sc_hd__clkbuf_8 sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_2",
"FAKEDIODE_CELL": "sky130_ef_sc_hd__fakediode_2",
"MAX_FANOUT_CONSTRAINT": "10",
"RE_BUFFER_CELL": "sky130_fd_sc_hd__buf_4",
"SYNTH_TIEHI_PORT": "sky130_fd_sc_hd__conb_1 HI",
"GPL_CELL_PADDING": "0",
"CLK_BUFFER": "sky130_fd_sc_hd__clkbuf_4",
"CLK_BUFFER_OUTPUT": "X",
"ROOT_CLK_BUFFER": "sky130_fd_sc_hd__clkbuf_16",
"SYNTH_DRIVING_CELL": "sky130_fd_sc_hd__inv_2",
"SYNTH_DRIVING_CELL_PIN": "Y",
"OUTPUT_CAP_LOAD": "33.442",
"TRISTATE_CELL_PREFIX": "sky130_fd_sc_hd__ebuf",
"LIB_FASTEST": "/pdk_root/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib",
"PLACE_SITE_WIDTH": "0.460",
"PLACE_SITE": "unithd",
"MAX_TRANSITION_CONSTRAINT": "0.75",
"FP_ENDCAP_CELL": "sky130_fd_sc_hd__decap_3",
"PLACE_SITE_HEIGHT": "2.720",
"DECAP_CELL": "sky130_ef_sc_hd__decap_12 sky130_fd_sc_hd__decap_8 sky130_fd_sc_hd__decap_6 sky130_fd_sc_hd__decap_4 sky130_fd_sc_hd__decap_3",
"CTS_ROOT_BUFFER": "sky130_fd_sc_hd__clkbuf_16",
"CTS_MAX_CAP": "1.53169",
"CELL_CLK_PORT": "CLK",
}
RAW_GF180MCUC_IN = {
"PDK_ROOT": "/pdk_root",
"PDK": "gf180mcuC",
"FP_PDN_HOFFSET": "16.65",
"GPIO_PADS_VERILOG": " /pdk_root/gf180mcuC/libs.ref/gf180mcu_io/verilog/GF018green_ipio_5p0c_75_5lm.v\n",
"STD_CELL_POWER_PINS": "VDD VNW",
"FP_IO_VLAYER": "Metal2",
"MAGIC_TECH_FILE": "/pdk_root/gf180mcuC/libs.tech/magic/gf180mcuC.tech",
"FP_PDN_VERTICAL_LAYER": "Metal4",
"GRT_LAYER_ADJUSTMENTS": "0,0,0,0,0",
"FP_PDN_CORE_RING_VWIDTH": "1.6",
"FP_PDN_HSPACING": "1.7",
"FP_PDN_VOFFSET": "16.32",
"LIB_SYNTH": "/pdk_root/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.lib",
"TECH_LEF_MAX": "/pdk_root/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/techlef/gf180mcu_fd_sc_mcu7t5v0__max.tlef",
"KLAYOUT_DEF_LAYER_MAP": "/pdk_root/gf180mcuC/libs.tech/klayout/tech/gf180mcu.map",
"MAGIC_MAGICRC": "/pdk_root/gf180mcuC/libs.tech/magic/gf180mcuC.magicrc",
"FULL_ADDER_MAP": "/pdk_root/gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/fa_map.v",
"RT_MAX_LAYER": "Metal5",
"VDD_PIN": "VDD",
"LIB_TYPICAL": "/pdk_root/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.lib",
"LIB_SLOWEST": "/pdk_root/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__ss_125C_4v50.lib",
"RCX_RULES_MAX": "/pdk_root/gf180mcuC/libs.tech/openlane/rules.openrcx.gf180mcuC.max",
"FP_PDN_HWIDTH": "1.6",
"DRT_MIN_LAYER": "Metal1",
"STD_CELL_GROUND_PINS": "VSS VPW",
"TRACKS_INFO_FILE": "/pdk_root/gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/tracks.info",
"TECH_LEF": "/pdk_root/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/techlef/gf180mcu_fd_sc_mcu7t5v0__nom.tlef",
"TECH_LEF_MIN": "/pdk_root/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/techlef/gf180mcu_fd_sc_mcu7t5v0__min.tlef",
"FP_PDN_HPITCH": "153.18",
"RCX_RULES": "/pdk_root/gf180mcuC/libs.tech/openlane/rules.openrcx.gf180mcuC.nom",
"STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
"FP_PDN_CORE_RING_VSPACING": "1.7",
"KLAYOUT_PROPERTIES": "/pdk_root/gf180mcuC/libs.tech/klayout/tech/gf180mcu.lyp",
"DRC_EXCLUDE_CELL_LIST": "/pdk_root/gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/drc_exclude.cells",
"CARRY_SELECT_ADDER_MAP": "/pdk_root/gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/csa_map.v",
"NO_SYNTH_CELL_LIST": "/pdk_root/gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/no_synth.cells",
"GPIO_PADS_LEF": " /pdk_root/gf180mcuC/libs.ref/gf180mcu_io/lef/GF018green_ipio_5p0c_75_5lm.lef\n",
"RIPPLE_CARRY_ADDER_MAP": "/pdk_root/gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/rca_map.v",
"RCX_RULES_MIN": "/pdk_root/gf180mcuC/libs.tech/openlane/rules.openrcx.gf180mcuC.min",
"CLOCK_WIRE_RC_LAYER": "Metal4",
"FP_TAPCELL_DIST": "20",
"SYNTH_LATCH_MAP": "/pdk_root/gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/latch_map.v",
"FP_PDN_VWIDTH": "1.6",
"MACRO_BLOCKAGES_LAYER": "Metal1 Metal2 Metal3 Metal4 Metal5",
"STD_CELL_LIBRARY_CDL": "/pdk_root/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/cdl/gf180mcu_fd_sc_mcu7t5v0.cdl",
"RT_MIN_LAYER": "Metal2",
"VDD_PIN_VOLTAGE": "5.00",
"FP_PDN_VPITCH": "153.6",
"DRC_EXCLUDE_CELL_LIST_OPT": "/pdk_root/gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/drc_exclude.cells",
"GDS_FILES": "/pdk_root/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/gds/gf180mcu_fd_sc_mcu7t5v0.gds",
"FP_PDN_RAIL_LAYER": "Metal1",
"KLAYOUT_TECH": "/pdk_root/gf180mcuC/libs.tech/klayout/tech/gf180mcu.lyt",
"FP_PDN_HORIZONTAL_LAYER": "Metal5",
"FP_PDN_CORE_RING_HOFFSET": "6",
"NETGEN_SETUP_FILE": "/pdk_root/gf180mcuC/libs.tech/netgen/gf180mcuC_setup.tcl",
"KLAYOUT_DRC_TECH_SCRIPT": "/pdk_root/gf180mcuC/libs.tech/klayout/drc/gf180mcu.drc",
"FP_PDN_VSPACING": "1.7",
"GND_PIN": "VSS",
"LIB_FASTEST": "/pdk_root/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__ff_n40C_5v50.lib",
"CELLS_LEF": "/pdk_root/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/lef/gf180mcu_fd_sc_mcu7t5v0.lef",
"TRISTATE_BUFFER_MAP": "/pdk_root/gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/tribuff_map.v",
"FP_PDN_RAIL_OFFSET": "0",
"FP_IO_HLAYER": "Metal3",
"FP_PDN_CORE_RING_HSPACING": "1.7",
"GND_PIN_VOLTAGE": "0.00",
"STD_CELL_LIBRARY_OPT": "gf180mcu_fd_sc_mcu7t5v0",
"FP_PDN_CORE_RING_HWIDTH": "1.6",
"DEF_UNITS_PER_MICRON": "2000",
"DATA_WIRE_RC_LAYER": "Metal2",
"METAL_LAYER_NAMES": "Metal1 Metal2 Metal3 Metal4 Metal5",
"FP_PDN_CORE_RING_VOFFSET": "6",
"PROCESS": "180",
"PL_LIB": "/pdk_root/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.lib",
"CELL_PAD_EXCLUDE": "gf180mcu_fd_sc_mcu7t5v0__filltie_* gf180mcu_fd_sc_mcu7t5v0__filldecap_* gf180mcu_fd_sc_mcu7t5v0__fill_* gf180mcu_fd_sc_mcu7t5v0__endcap_*",
"SYNTH_MIN_BUF_PORT": "gf180mcu_fd_sc_mcu7t5v0__buf_1 I Z",
"DIODE_CELL": "gf180mcu_fd_sc_mcu7t5v0__antenna",
"SYNTH_CLK_DRIVING_CELL_PIN": "ZN",
"SYNTH_TIELO_PORT": "gf180mcu_fd_sc_mcu7t5v0__tiel ZN",
"FP_PDN_RAIL_WIDTH": "0.6",
"FP_WELLTAP_CELL": "gf180mcu_fd_sc_mcu7t5v0__filltie",
"FILL_CELL": "gf180mcu_fd_sc_mcu7t5v0__fill_*",
"DPL_CELL_PADDING": "0",
"DIODE_CELL_PIN": "I",
"CTS_CLK_BUFFER_LIST": "gf180mcu_fd_sc_mcu7t5v0__clkbuf_2 gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 gf180mcu_fd_sc_mcu7t5v0__clkbuf_8",
"MAX_FANOUT_CONSTRAINT": "10",
"SYNTH_CLK_DRIVING_CELL": "gf180mcu_fd_sc_mcu7t5v0__inv_4",
"SYNTH_TIEHI_PORT": "gf180mcu_fd_sc_mcu7t5v0__tieh Z",
"GPL_CELL_PADDING": "0",
"SYNTH_DRIVING_CELL": "gf180mcu_fd_sc_mcu7t5v0__inv_1",
"SYNTH_DRIVING_CELL_PIN": "ZN",
"OUTPUT_CAP_LOAD": "72.91",
"TRISTATE_CELL_PREFIX": "gf180mcu_fd_sc_mcu7t5v0__bufz",
"DIODE_INSERTION_STRATEGY": "4",
"PLACE_SITE_WIDTH": "0.56",
"PLACE_SITE": "GF018hv5v_mcu_sc7",
"MAX_TRANSITION_CONSTRAINT": "3",
"FP_ENDCAP_CELL": "gf180mcu_fd_sc_mcu7t5v0__endcap",
"PLACE_SITE_HEIGHT": "3.92",
"DECAP_CELL": "gf180mcu_fd_sc_mcu7t5v0__fillcap_*",
"CTS_ROOT_BUFFER": "gf180mcu_fd_sc_mcu7t5v0__clkbuf_16",
"CTS_MAX_CAP": "0.5",
}
def test_pdk_migration_basics():
from openlane.config.pdk_compat import migrate_old_config
sky130A_migrated = migrate_old_config(RAW_SKY130A_IN)
gf180mcuC_migrated = migrate_old_config(RAW_GF180MCUC_IN)
for pdk_name, pdk_migrated in [
("sky130A", sky130A_migrated),
("gf180mcuC", gf180mcuC_migrated),
]:
for bad_variable in [
"SYNTH_DRIVING_CELL_PIN",
"SYNTH_TIEHI_PORT",
"SYNTH_TIELO_PORT",
"SYNTH_MIN_BUF_PORT",
"DIODE_CELL_PIN",
"RCX_RULES",
"RCX_RULES_MIN",
"RCX_RULES_MAX",
"TECH_LEF",
"TECH_LEF_MIN",
"TECH_LEF_MAX",
"SYNTH_CAP_LOAD",
]:
assert (
bad_variable not in pdk_migrated
), f"OL2-incompatible variable {bad_variable} survived migration script for {pdk_name}"
for cell_variable in [
"SYNTH_DRIVING_CELL",
"SYNTH_TIEHI_CELL",
"SYNTH_BUFFER_CELL",
"DIODE_CELL",
]:
assert (
cell_variable in pdk_migrated
), f"required variable {cell_variable} missing from migrated object for sky130"
assert (
"/" in pdk_migrated[cell_variable]
), f"required variable {cell_variable} has invalid value: {pdk_migrated[cell_variable]}"
f3aa9354aThis file is pinned to the selected release. Download the original to open it in your design tool.