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librelane

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Mohamed GaberCleanup, update submodulef3aa9354a

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{
    "DESIGN_NAME": "user_project_wrapper",
    "VERILOG_FILES": [
        "dir::./defines.v",
        "dir::./SPM_example.v",
        "dir::./user_project_wrapper.v"
    ],
    "CLOCK_PERIOD": 25,
    "CLOCK_PORT": "wb_clk_i",
    "FP_CORE_UTIL": 5
}