Liberty74: An Open-Source Verilog-to-PCB Flow

Liberty74 is a fully open-source Verilog-to-PCB Flow.

Disclaimer

This project is still under active development; some parts may not yet be fully functional, and existing interfaces, toolflows, and conventions may be broken without prior notice.

Dependencies

Liberty74 makes use of the following open-source projects:

Synthesis and Layout

• Yosys: Synthesis
• OpenROAD: Layout
• KiCad: PCB
• Basilisk: Synthesis Strategy

PDK Generator and other utilities

• lef def parser library: modified, see utils/lef_def_parser
• KiUtils: KiCad File Parser Library
• Mako: Template Library
• Bender: HW Dependency Manager

Linters

• tcllint: TCL Linter
• pylint: Python Linter
• yamllint: YAML Linter
• mdl: Markdown Linter
• Verible: Verilog Linter
• JSON lint: JSON Linter
• pulp actions: CI License Linter

Documentation - Basic Usage

Generate PDK

To generate the PDK files use:

make gen-pdk

Synthesis

To synthesize your RTL into a netlist use:

make synth

Layout

To layout your design use:

make chip

Convert to PCB

To convert your layout to a KiCad-PCB use:

make pcb

Linting

To lint all languages use:

make lint-all

You can also lint each language seperately:

make lint-yaml
make lint-tcl
make lint-python
make lint-json
make lint-verilog
make lint-markdown

Clean

To clean use:

make clean

License

Liberty74 is released under a permissive license.
All hardware sources and tool scripts are licensed under Solderpad v0.51 (SHL-0.51) see LICENSE
All software sources are licensed under Apache 2.0 (Apache-2.0) see Apache-2.0

Exceptions:

• utils/lef_def_parser is licensed under MIT (MIT) see utils/lef_der_parser
  Original Author ©Tri Minh Cao, see https://github.com/trimcao/lef-parser

Contributing

We are happy to accept pull requests and issues from any contributors.
See CONTRIBUTING.md for additional information.