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JSilicon

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Design files

mirseo[DOCS/readme] Chip Arrival and Project Status Update. - Everyone, this is the final call. Thank you for your interest and support for this project. - Thank you. Really.ad084f1a0

Name	Storage	Size
.. / Parent directory
jsilicon_agent.sv	Git	1.7 KB
jsilicon_driver.sv	Git	1.9 KB
jsilicon_env.sv	Git	1.0 KB
jsilicon_if.sv	Git	1.4 KB
jsilicon_monitor.sv	Git	2.0 KB
jsilicon_pkg.sv	Git	599 B
jsilicon_scoreboard.sv	Git	4.1 KB
jsilicon_sequences.sv	Git	9.1 KB
jsilicon_tb_top.sv	Git	1.5 KB
jsilicon_test.sv	Git	7.3 KB
jsilicon_transaction.sv	Git	4.0 KB
Makefile	Git	4.5 KB
QUICKSTART.md	Git	4.4 KB
README.md	Git	9.2 KB
run.sh	Git	6.0 KB
setup_vcs.csh	Git	3.2 KB
simv.log	Git	35.5 KB
vc_hdrs.h	Git	13.2 KB

Name	Storage	Size
.. / Parent directory
jsilicon_agent.sv	Git	1.7 KB
jsilicon_driver.sv	Git	1.9 KB
jsilicon_env.sv	Git	1.0 KB
jsilicon_if.sv	Git	1.4 KB
jsilicon_monitor.sv