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Commits included in published releases. Unpublished intermediate commits are private. Showing matches from the latest 100 commits ending at this release.

Kludgey delay added to make wishbone writes work. On reads, WB was acking before data latched, added a delay to prevent this. TODO go back and fix (add fifo ack or something).

jess b · Apr 8, 2012, 8:55 AM UTC

73cb7e6b103f

Reads out only one col instead of 3. Probably breaks SDRAM spec, but works for now.

jess b · Apr 8, 2012, 8:46 AM UTC

2e3ab234f0a4

Works-ish, still reading too many cols. First col read is correct, but subsequent reads have no data so FSMC gets xxxx.

jess b · Apr 8, 2012, 8:22 AM UTC

5a5c80fd83b1

Changed address-passing triggers. Was encountering some timing issues with write_en and read_en signals, now they get passed up from a lower module.

jess b · Apr 8, 2012, 8:10 AM UTC

1f9d7dca1be4

Added WRITE recovery delay.

jess b · Apr 8, 2012, 5:30 AM UTC

bd65c5c64377

Removed Xilinx/Micron files.

jess b · Apr 5, 2012, 11:37 AM UTC

37839722783b

Runs! Functionality still broken, though.

jess b · Apr 5, 2012, 11:32 AM UTC

a7ff8f5272a8

Added unisims files.

jess b · Apr 5, 2012, 11:18 AM UTC

5bb2cf4b06db

Compiles, still throws warnings, no tests

jess b · Apr 5, 2012, 11:17 AM UTC

e4d6c26fef4d

Cleanup.

jess b · Apr 4, 2012, 8:19 PM UTC

1751a84cd2f4

Initial commit; nonfunctional kludge of cores.

jess b · Apr 4, 2012, 8:17 PM UTC

775ea2b5215a

Fixed incorrect TB in FSMC core.

jess b · Mar 26, 2012, 5:12 PM UTC

dcb29a0b2485

Added oakfsmc core.

jess b · Jan 9, 2012, 9:32 PM UTC

0d8edb330a6f

Initial commit.

jess b · Jan 9, 2012, 9:25 PM UTC

f871358e1919