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hackrf

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Things Files Issues Pull requests Builds · 0 Commits

fix-pll-reset

OTP_USB_IDsb6d987ee4

alt-ref-freq27fe1a2c5

antoinevg/bitstream-supported-operationsfed238147

antoinevg/bitstream-supported-valuesc3e03945d

antoinevg/catch-ram-overruna3ab28c36

antoinevg/radio-config-mode6bfe25981

antoinevg/radio-fp253c1a65d

antoinevg/radio-hackrf-transfere15fe9081

antoinevg/register-lockf657bedc7

clk-cie5e5fbdbe

clkin-wip1945fca07

cpld-cleanup3d517954c

fix-17995ccc441c4

fix-mixer-lock16355f8e5

fix-pll-reset · selected1c29079fa

fix-radio-config-gain0cf5cc229

flush-callback45504ff39

fpga-clock-phased2e499056

h1r9b1d1fd4ac

harmonyc24f1cf2a

jenkins-functions601a77a9d

main7f96cc8e3

mcu-pll-b9153f3d55

portapack-detection092d034d8

stdout8ce544579

thingatlas/importb29854900

transfer-single-ci0299f70a3

universal-hil-fixe1dc05281

universal-rebase-experimental2ad78ce6d

Loading revisions…1c29079fa

Repository files

.github
ci-scripts
docs
firmware
hardware
host
tools
.clang-format
.gitattributes
.gitignore
.gitmodules
.readthedocs.yaml
CODE_OF_CONDUCT.md
COPYING
Dockerfile
Jenkinsfile
Readme.md
TRADEMARK

Design files

Repository / firmware / tools

Commit history

Michael OssmannReset only sample clock outputs when changing rate1c29079fa

Name	Storage	Size
.. / Parent directory
check_clock.py	Git	1.9 KB
cpld_bitstream.py	Git	10.2 KB
dumb_crc32.py	Git	582 B
dump_cgu.py	Git	6.7 KB
xsvf.py	Git	4.4 KB

Repository / firmware / tools

Commit history

Name	Storage	Size
.. / Parent directory
check_clock.py	Git	1.9 KB
cpld_bitstream.py	Git	10.2 KB
dumb_crc32.py	Git	582 B
dump_cgu.py