fpga-tidbits

EMULATOR_BIN:=emu
TRACE ?= false
VERILATOR_SRC_DIR=/usr/share/verilator/include
VERIlATOR_SRC_GEN_DIR=verilated
VERILATOR_OPTIONS=-Iother-verilog -Wno-assignin -Wno-fatal -Wno-lint -Wno-style -Wno-COMBDLY -Wno-STMTDLY
TARGET_LIB=tidbits.a
VER_BUILD_DIR=obj_dir

ifeq ($(TRACE),true)
  VERILATOR_OPTIONS += --trace
  CC_OPTIONS := -CFLAGS "-DTRACE"
endif

PLATFORM := TesterWrapper
SRCS=main.cpp platform-verilatedtester.cpp

build: $(EMULATOR_BIN)

lib: $(SRCS)
	verilator --cc $(PLATFORM).v $(VERILATOR_OPTIONS) $(CC_OPTIONS) --exe --build $^
	@rm $(VER_BUILD_DIR)/main.o
	ar -rcs $(TARGET_LIB) $(VER_BUILD_DIR)/*.o

$(EMULATOR_BIN): main.cpp platform-verilatedtester.cpp
	@verilator --cc $(PLATFORM).v $(VERILATOR_OPTIONS) $(CC_OPTIONS) --exe --build main.cpp platform-verilatedtester.cpp
	@cp obj_dir/V$(PLATFORM) $(EMULATOR_BIN)

clean:
	@rm -rf obj_dir
	@rm -f $(EMULATOR_BIN)

rebuild: clean build

run: build
	@./$(EMULATOR_BIN)

.PHONY: build clean rebuild run